Double-node upsets induced by the charge sharing effects are emerging as a major
reliability issue in nanometer latch design. Although the existing robust latches can provide …

Single event upsets (SEUs) that affect adjacent nodes in a design, by charge sharing
mechanisms among these nodes, are a great concern in nanometer SRAMs, since pairs of …

In this paper, we propose a novel high reliability and low cost DNU (Double Node Upset)
tolerant latch, HRCE (High Robust and Cost Effective) latch, for nanoscale CMOS …

In this paper, a self-recoverable, frequency-aware and cost-effective robust latch (referred to
as RFC) is proposed in 45nm CMOS technology. By means of triple mutually feedback …

With the continuous scaling of feature sizes, latches are becoming more and more sensitive
to the multiple-node upsets (MNUs) induced by radiation. Based on input-split C-elements …

Latches areused extensivelyin digital circuits; however, as technology scaling reaches
nanometric feature sizes, externally induced phenomena (such as radiation strikes in …

As technology node entered the era of nanotechnology, a latch is much more susceptible to
soft errors caused by energetic particles in space radiation environment. In order to enhance …

This paper presents an Interconnection heterogeneous and High-speed Triple-node-upset
Recovery Latch (IHTRL). This latch utilizes homogeneous elements to construct a 4× 4 array …

With the continuous scaling of CMOS feature sizes, single event triple-node-upset (TNU)
induced by charge sharing has become a serious reliability issue. This paper presents a low …

Energy efficiency is considered to be the most critical design parameter for IoT and other
ultra low power applications. However, energy efficient circuits show a lesser immunity …