SRAM suffers read-disturb and write failures at a low supply voltage, especially at deep
subthreshold operation. This study proposes a 9T-SRAM cell with a data-aware-feedback …

Low power 3D-IC is well-suited to mobile systems; however, it poses a number of
challenges associated with thermal stress, particularly in designs with many stacked layers …

In this paper, approximate SRAMs are explored in the context of error-tolerant applications,
in which energy is saved at the cost of the occurrence of read/write errors (ie, signal quality …

Due to global and local process variations, on-chip SRAM suffers failures at a low supply
voltage (VDD). This study proposes a differential data-aware power-supplied D 2 AP 8T …

The use of low voltage circuits and power-off mode help to reduce the power consumption of
chips. Non-volatile logic (nvLogic) and nonvolatile SRAM (nvSRAM) enable a chip to …

This paper presents a performance comparison of a carbon nanotube-based field effect
(CNFET)-and CMOS-based 6T SRAM cell at the 32nm technology node. HSPICE …

A leakage current compensation design for nanoscale SRAMs is proposed in this paper.
The proposed compensation design is composed of a leakage current sensor, which …

An ultra‐low‐energy SRAM composed of single‐ended cells is demonstrated on silicon in
this investigation. More specifically, the supply voltages of cells are gated by wordline (WL) …

This article proposes a CNFET 10T SRAM cell based on Stanford Virtual Source model at 5
nm technology node, through optimization design and simulation analysis to select optimum …

Background/Objectives: In the contemporary era, due to the rapid development in various
low power VLSI circuits, the primary factors that affect the performance of the circuits are …