Secure memory control parameters in table look aside buffer data fields and support memory array
WE Hall - US Patent 8,954,751, 2015 - Google Patents
(*) Notice: Subject to any disclaimer, the term of this 2003, 0005279 A1 1/2003 Valenci et
al...... T13, 150 patent is extended or adjusted under 35 2003/00 18908 A1 1/2003 Mercer et …
al...... T13, 150 patent is extended or adjusted under 35 2003/00 18908 A1 1/2003 Mercer et …
An energy efficient TLB design methodology
This paper researches Translation Look-aside Buffer (TLB) of embedded processor. Based
on an analysis of design-related factors: power, area, critical path and performance of our …
on an analysis of design-related factors: power, area, critical path and performance of our …
A model-driven graph-matching approach for design pattern detection
ML Bernardi, M Cimitile… - 2013 20th Working …, 2013 - ieeexplore.ieee.org
In this paper an approach to automatically detect Design Patterns (DPs) in Object Oriented
systems is presented. It allows to link system's source code components to the roles they …
systems is presented. It allows to link system's source code components to the roles they …
Compiler-directed code restructuring for reducing data TLB energy
M Kandemir, I Kadayif, G Chen - Proceedings of the 2nd IEEE/ACM/IFIP …, 2004 - dl.acm.org
Prior work on TLB power optimization considered circuit and architectural techniques. A
recent software-based technique for data TLBs has considered the possibility of storing the …
recent software-based technique for data TLBs has considered the possibility of storing the …
Low-power high-performance NAND match line content addressable memories
V Chaudhary, LT Clark - IEEE transactions on very large scale …, 2006 - ieeexplore.ieee.org
Content addressable memory (CAM) is used in fully associative VLSI lookup circuits for
cache memory, translation lookaside buffers (TLBs), and in Internet Protocol (IP) address …
cache memory, translation lookaside buffers (TLBs), and in Internet Protocol (IP) address …
Reducing data TLB power via compiler-directed address generation
I Kadayif, P Nath, M Kandemir… - IEEE Transactions on …, 2007 - ieeexplore.ieee.org
Address translation using the translation lookaside buffer (TLB) consumes as much as 16%
of the chip power on some processors because of its high associativity and access …
of the chip power on some processors because of its high associativity and access …
[PDF][PDF] 通用处理器的高带宽访存流水线研究
张浩， 林伟， 周永彬， 叶笑春， 范东睿 - 计算机学报, 2009 - cjc.ict.ac.cn
摘要存储器访问速度的发展远远跟不上处理器运算速度的发展, 日益严峻的访存速度问题严重
制约了处理器速度的进一步发展. 降低load to use 延迟是提高处理器访存性能的关键 …
制约了处理器速度的进一步发展. 降低load to use 延迟是提高处理器访存性能的关键 …
Optimizing instruction TLB energy using software and hardware techniques
I Kadayif, A Sivasubramaniam, M Kandemir… - ACM Transactions on …, 2005 - dl.acm.org
Power consumption and power density for the Translation Look-aside Buffer (TLB) are
important considerations not only in its design, but can have a consequence on cache …
important considerations not only in its design, but can have a consequence on cache …
Synonymous address compaction for energy reduction in data TLB
CS Ballapuram, HHS Lee, M Prvulovic - Proceedings of the 2005 …, 2005 - dl.acm.org
Modern processors can issue and execute multiple instructions per cycle, often performing
multiple memory operations simultaneously. To reduce stalls due to resource conflicts, most …
multiple memory operations simultaneously. To reduce stalls due to resource conflicts, most …