Abstract Circuit Aging Reliability Analysis Tool (CARAT), a framework that calculates
random activity (frequency and duty) aware degradation of FETs to simulate circuit aging …

As feature sizes of transistors began to approach atomic levels, aging effects have become
one of major concerns when it comes to reliability. Recently, aging effects have become a …

DVFS-based boosting techniques have been widely employed by commercial multi-core
processors, due to their superiority in improving the performance. Boosting, however, is …

The continuous scaling of transistor dimensions has increased the sensitivity of digital
circuits to PVT variations and, more recently, to aging effects such as BTI and HCI. Large …

28nm Gate First High-K Metal Gate (GF-HKMG) technology is analyzed for Hot-Carrier
Degradation (HCD) under varying gate/drain (VG/VD) bias and temperature (T: 300K to …

Bias Temperature Instability (BTI) under sub-microsecond DVFS transients manifests as
instantaneous frequency degradation and recovery that has been predicted in past literature …

A SPICE compatible compact model is proposed for the time kinetics of threshold voltage
shift (ΔV_T) due to Hot Carrier Degradation (HCD) and Bias Temperature Instability (BTI) …

Circuit aging has become the major reliability concern in current and upcoming technology
nodes. For instance, Bias Temperature Instability (BTI) leads to an increase in the threshold …

Die Gewährleistung der Zuverlässigkeit von CMOS-Schaltungen ist derzeit eines der
größten Herausforderungen beim Chip-und Schaltungsentwurf. Mit dem Ende der Dennard …

Driven by the ever-increasing performance demand, multicore processors have emerged
enabling concurrent computations on a single chip. A multicore processor can be exploited …