[图书][B] System-on-chip test architectures: nanometer design for testability

LT Wang, CE Stroud, NA Touba - 2010 - books.google.com
Modern electronics testing has a legacy of more than 40 years. The introduction of new
technologies, especially nanometer technologies with 90nm or smaller geometry, has …

Fast and memory efficient mining of high utility itemsets in data streams

HF Li, HY Huang, YC Chen, YJ Liu… - 2008 eighth IEEE …, 2008 - ieeexplore.ieee.org
Efficient mining of high utility itemsets has become one of the most interesting data mining
tasks with broad applications. In this paper, we proposed two efficient one-pass algorithms …

Low-cost test of embedded RF/analog/mixed-signal circuits in SOPs

SS Akbay, A Halder, A Chatterjee… - IEEE Transactions on …, 2004 - ieeexplore.ieee.org
Increasing levels of integration and high speeds of operation have made the problem of
testing complex systems-on-packages (SOPs) very difficult. Testing packages with …

Fault diagnosis of analog circuits based on machine learning

K Huang, HG Stratigopoulos… - 2010 Design, Automation & …, 2010 - ieeexplore.ieee.org
We discuss a fault diagnosis scheme for analog integrated circuits. Our approach is based
on an assemblage of learning machines that are trained beforehand to guide us through …

Multi-tone testing of linear and nonlinear analog circuits using polynomial coefficients

S Sindia, V Singh, VD Agrawal - 2009 Asian test symposium, 2009 - ieeexplore.ieee.org
A method of testing for parametric faults of analog circuits based on a polynomial
representation of fault-free function of the circuit is presented. The response of the circuit …

Parametric fault diagnosis for analog circuits using a Bayesian framework

F Liu, PK Nikolov, S Ozev - 24th IEEE VLSI Test Symposium, 2006 - ieeexplore.ieee.org
In this paper, we present a parametric fault diagnosis approach for analog/RF circuits based
on a Bayesian framework. The Bayesian fault diagnosis requires extensive statistical …

Optimized multitone test stimulus driven diagnosis of RF transceivers using model parameter estimation

A Banerjee, V Natarajan, S Sen… - … Conference on VLSI …, 2011 - ieeexplore.ieee.org
Test time and test complexity reduction has become a critical challenge in modern RF
testing. Prior “alternative” test methods have achieved fast testing at the cost of using …

Polynomial coefficient based DC testing of non-linear analog circuits

S Sindia, V Singh, VD Agrawal - Proceedings of the 19th ACM Great …, 2009 - dl.acm.org
DC testing of parametric faults in non-linear analog circuits based on polynomial
approximation of the functionality of fault free circuit is presented. Classification of circuit …

Method for diagnosing process parameter variations from measurements in analog circuits

A Chatterjee, S Cherubal - US Patent 6,625,785, 2003 - Google Patents
A method for diagnosing process parameter variations from measurements in analog
circuits. The diagnosability conditions for the accurate computation of device parameters are …

Test generation algorithm for analog systems based on support vector machine

T Long, H Wang, B Long - Signal, image and video processing, 2011 - Springer
In some methods for test generation, an analog device under test (DUT) is treated as a
discrete-time digital system by placing it between a digital-to-analog converter and an …