This thesis involves modeling, design, Hardware Description Language (HDL) design capture, synthesis, implementation and HDL virtual prototype simulation validation of an …
1 CURRICULUM VITAE J. Robert Heath Department of Electrical and Computer Engineering University of Kentucky Lexington, KY 40506 Page 1 1 CURRICULUM VITAE J. Robert Heath …
[引用][C]A New Processor-to-Memory Crossbar Interconnect Network with a Variable Priority Memory Contention Resolution Protocol for Multiprocessor Architectures
V Duvvuri, JR Heath, K Bhide, S Hegde - Proceedings of the 2005 International Conference …