[PDF][PDF] Functional Enhancement and Applications Development for a Hybrid, Heterogeneous Single-Chip Multiprocessor Architecture

S Hegde - 2004 - uknowledge.uky.edu
Reconfigurable and dynamic computer architecture is an exciting area of research that is
rapidly expanding to meet the requirements of compute intense real and non-real time …

[PDF][PDF] Design Enhancement and Integration of a Processor-Memory Interconnect Network into a Single-Chip Multiprocessor Architecture

KP Bhide - 2004 - core.ac.uk
This thesis involves modeling, design, Hardware Description Language (HDL) design
capture, synthesis, implementation and HDL virtual prototype simulation validation of an …

[PDF][PDF] PROFESSIONAL EMPLOYMENT AND AFFILIATIONS

JR Heath - 2012 - ism.engr.uky.edu
1 CURRICULUM VITAE J. Robert Heath Department of Electrical and Computer Engineering
University of Kentucky Lexington, KY 40506 Page 1 1 CURRICULUM VITAE J. Robert Heath …

[引用][C] A New Processor-to-Memory Crossbar Interconnect Network with a Variable Priority Memory Contention Resolution Protocol for Multiprocessor Architectures

V Duvvuri, JR Heath, K Bhide, S Hegde - Proceedings of the 2005 International Conference …