Impact of temperature variation on noise parameters and HCI degradation of Recessed Source/Drain Junctionless Gate All Around MOSFETs

A Kumar, TK Gupta, BP Shrivastava, A Gupta - Microelectronics Journal, 2023 - Elsevier
With the continuous scaling for MOS device, the noise parameters has becoming a critical
parameter. The noise performance of an electronic device can be measured with the help of …

Work function engineering with linearly graded binary metal alloy gate electrode for short-channel SOI MOSFET

S Deb, NB Singh, N Islam… - IEEE transactions on …, 2011 - ieeexplore.ieee.org
Over the last few decades, silicon-on-insulator (SOI) technology has been identified as one
possible solution for enhancing the performance of CMOS because of its numerous …

Noise and linearity analysis of recessed-source/drain junctionless Gate All Around (Re-S/D-JL-GAA) MOSFETs for communication systems

A Kumar, TK Gupta, BP Shrivastava, A Gupta - Microelectronics Journal, 2023 - Elsevier
Noise becomes a critical performance for any electronic component when it is being used for
communication systems, it makes MOSFETs less effective at performing their functions in a …

Dual metal gate tunneling field effect transistors based on MOSFETs: a 2-D analytical approach

Z Ramezani, AA Orouji - Superlattices and Microstructures, 2018 - Elsevier
A novel 2-D analytical drain current model of novel Dual Metal Gate Tunnel Field Effect
Transistors Based on MOSFETs (DMG-TFET) is presented in this paper. The proposed …

A two dimensional analytical modeling of surface potential in triple metal gate (TMG) fully-depleted Recessed-Source/Drain (Re-S/D) SOI MOSFET

A Priya, RA Mishra - Superlattices and Microstructures, 2016 - Elsevier
In this paper, analytical modeling of surface potential is proposed for new Triple Metal Gate
(TMG) fully depleted Recessed-Source/Dain Silicon On Insulator (SOI) Metal Oxide …

An analytical threshold voltage model for a short-channel dual-metal-gate (DMG) recessed-source/drain (Re-S/D) SOI MOSFET

GK Saramekala, A Santra, S Dubey, S Jit… - Superlattices and …, 2013 - Elsevier
In this paper, an analytical short-channel threshold voltage model is presented for a dual-
metal-gate (DMG) fully depleted recessed source/drain (Re-S/D) SOI MOSFET. For the first …

A threshold voltage model of short-channel fully-depleted recessed-source/drain (Re-S/D) UTB SOI MOSFETs including substrate induced surface potential effects

A Kumar, PK Tiwari - Solid-state electronics, 2014 - Elsevier
In this paper, a threshold voltage model of short-channel recessed-source/drain (Re-S/D)
ultra-thin body (UTB) SOI MOSFETs has been presented considering the substrate induced …

A charge-plasma-based dual-metal-gate recessed-source/drain dopingless junctionless transistor with enhanced analog and RF performance

PK Verma, YK Verma, V Mishra, SK Gupta - Journal of Computational …, 2020 - Springer
A distinctive charge plasma approach is used to propose a novel dual-metal-gate (DMG)
recessed-source/drain dopingless junctionless transistor (Re S/D DLJLT) in which the …

Design of high speed and low-power ring oscillator circuit in recessed source/drain SOI technology

A Priya, NA Srivastava, RA Mishra - ECS Journal of Solid State …, 2019 - iopscience.iop.org
In this paper, switching speed of CMOS inverter and Ring Oscillator is analyzed for the first
time using Triple-Metal-Gate (TMG) Recessed-Source/Drain (Re-S/D) SOI MOSFET. Re-S/D …

Analysis and modeling of unipolar junction transistor with excellent performance: a novel DG MOSFET with junction

Z Ramezani, AA Orouji - Journal of Computational Electronics, 2018 - Springer
We propose herein a new dual-gate metal–oxide–semiconductor field-effect transistor
(MOSFET) with just a unipolar junction (UJ-DG MOSFET) on the source side. The UJ-DG …