This paper presents CMP Cooperative Caching, a unified framework to manage a CMP's
aggregate on-chip cache resources. Cooperative caching combines the strengths of private …

Shared last-level caches, widely used in chip-multi-processors (CMPs), face two
fundamental limitations. First, the latency and energy of shared caches degrade as the …

A key determinant of overall system performance and power dissipation is the cache
hierarchy since access to off-chip memory consumes many more cycles and energy than on …

Cache hierarchies are increasingly non-uniform and difficult to manage. Several techniques,
such as scratchpads or reuse hints, use static information about how programs access data …

With the rapid development of mobile communication technology and intelligent
applications, the quantity of mobile devices and data traffic in networks have been growing …

Next generation tiled microarchitectures are going to be limited by off-chip misses and by on-
chip network usage. Furthermore, these platforms will run an heterogeneous mix of …

The rise of general-purpose computing on GPUs has influenced architectural innovation on
them. The introduction of an on-chip cache hierarchy is one such innovation. High L1 miss …

This paper describes computational models for particle-laden flows based on a fully
resolved fluid-structure interaction. The flow simulation uses the Lattice Boltzmann method …

Caching is an important optimization in search engine architectures. Existing caching
techniques for search engine optimization are mostly biased towards the reduction of …

As more processing cores are integrated into one chip and feature size continues to shrink,
the average access latency for remote nodes using directory-based coherence protocol …