High-speed hybrid multiplier design using a hybrid adder with FPGA implementation
V Thamizharasan, N Kasthuri - IETE Journal of Research, 2023 - Taylor & Francis
The major role of electronic devices is providing low power dissipation and high speed with
compact area. The speed of electronic devices depends on arithmetic operations …
compact area. The speed of electronic devices depends on arithmetic operations …
Efficient 2D DCT architecture based on approximate compressors for image compression with HEVC intra-prediction
This study presents a design of two-dimensional (2D) discrete cosine transform (DCT)
architecture to be used with high-efficiency video coding (HEVC) intra-prediction method in …
architecture to be used with high-efficiency video coding (HEVC) intra-prediction method in …
A 16 nm finfet circuit with triple function as digital multiplexer, active-high and active-low output decoder for high-performance sram architecture
This paper presents a fin field-effect transistor (FinFET)-based single circuit (FSC) used to
realize an active-high output decoder (AHD), active-low output decoder (ALD) and digital …
realize an active-high output decoder (AHD), active-low output decoder (ALD) and digital …
FPGA implementation of proficient Vedic multiplier architecture using hybrid carry select adder
V Thamizharasan, N Kasthuri - International Journal of Electronics, 2024 - Taylor & Francis
Nowadays, the application of computations and communications is needed for high
performance, reduced size and lower power utilisation. The multiply and add functions are …
performance, reduced size and lower power utilisation. The multiply and add functions are …
Design of 2-1 Multiplexer based high-speed, Two-Stage 90 nm Carry Select Adder for fast arithmetic units
This paper proposes a new Two-Stage Carry Select Adder (TSCSA) using a single type of
leaf cell ie, a 2-1 Multiplexer. All the existing Carry Select Adders (CaSeAs) are constructed …
leaf cell ie, a 2-1 Multiplexer. All the existing Carry Select Adders (CaSeAs) are constructed …
A 90 nm area and power efficient Carry Select Adder using 2–1 multiplexer based Excess-1 block
This paper proposes a novel architecture of excess-1 adder-based Carry Select Adder
(M2CSA) using single leaf cell ie, 2–1 Multiplexer. M2CSA is designed using a new type of …
(M2CSA) using single leaf cell ie, 2–1 Multiplexer. M2CSA is designed using a new type of …
Design of 0.8 V, 22 nm DG-FinFET based efficient VLSI multiplexers
Conventional CMOS has become successful logic for most digital VLSI circuits and a good
candidate in terms of power dissipation. But due to its dual nature, more transistors are …
candidate in terms of power dissipation. But due to its dual nature, more transistors are …
Design of power efficient Vedic multiplier using adiabatic logic
K Dutta, S Chattopadhyay, V Biswas… - 2019 International …, 2019 - ieeexplore.ieee.org
Various “arithmetic operations”,“signal and image processing systems” and “communication
devices” incorporate multipliers as the basic element. Vedic mathematics is an ancient …
devices” incorporate multipliers as the basic element. Vedic mathematics is an ancient …
Design of a 4-Bit 4-Operand Adder Using Verilog: An Abstraction Analysis
A Chopde, J Kale, R Kamble… - 2024 IEEE International …, 2024 - ieeexplore.ieee.org
With an increasing demand for efficient computational systems, the analysis is needed to
address the challenge of developing a multi-operand adder capable of processing multi …
address the challenge of developing a multi-operand adder capable of processing multi …
Design of approximate discrete cosine transform architecture for image compression with HEVC intra prediction
Discrete cosine transform (DCT) is an integral part of many image compression standards.
Image compression with HEVC inra prediction method also uses DCT. Because the …
Image compression with HEVC inra prediction method also uses DCT. Because the …