WO2018142140A1 - Branch target buffer for a data processing apparatus - Google Patents
WO2018142140A1 - Branch target buffer for a data processing apparatus - Google Patents …

Abstract Systems and methods are disclosed for fetch stage handling of indirect jumps in a
processor pipeline. For example, a method includes detecting a sequence of instructions …

A unified queue configured to perform decoupled prediction and fetch operations, and
related apparatuses, systems, methods, and computer-readable media, is disclosed. The …

Reusing fetched, flushed instructions after an instruction pipeline flush in response to a
hazard in a processor to reduce instruction re-fetching is disclosed. An instruction …

A microprocessor is shown, in which a branch predictor and an instruction cache are
decoupled by a fetch-target queue (FTQ). The branch predictor performs branch prediction …

A microprocessor with a solution to instruction fetching failure is shown. The branch
predictor and the instruction cache are decoupled by a fetch target queue. In response to …

A microprocessor is shown, in which a branch predictor and an instruction cache are
decoupled by a fetch-target queue (FTQ). The FTQ stores at least an instruction address …

Systems and methods are disclosed for fetch stage handling of indirect jumps in a processor
pipeline. For example, a method includes detecting a sequence of instructions fetched by a …