A novel high-speed approach for 16× 16 Vedic multiplication with compressor adders
Y Bansal, C Madhu - Computers & Electrical Engineering, 2016 - Elsevier
In this paper, a novel architecture of Vedic multiplier with 'Urdhava-tiryakbhyam'methodology
for 16 bit multiplier and multiplicand is proposed with the use of compressor adders …
for 16 bit multiplier and multiplicand is proposed with the use of compressor adders …
New current-mode multipliers by CNTFET-based n-valued binary converters
This paper presents new Binary Converters (or current-mode compressors) by the usage of
carbon nanotube field effect transistors. The new designs are made of three parts: 1) the …
carbon nanotube field effect transistors. The new designs are made of three parts: 1) the …
A circuit-level methodology for leakage power reduction of high-efficient compressors in 22-nm CMOS technology
A new circuit-level methodology called input controlled leakage restrainer transistor (ICLRT)
compatible with single threshold CMOS technology is proposed in this paper, to further …
compatible with single threshold CMOS technology is proposed in this paper, to further …
CMOS Implementation of a Novel High Speed 4: 2 Compressor for Fast Arithmetic Circuits
M Ghasemzadeh, N Mohabbatian… - IETE Journal of …, 2023 - Taylor & Francis
This paper deals with the design and analysis of a new 4-2 compressor which can be used
in high-speed multipliers. The proposed compressor features eliminated glitch at the output …
in high-speed multipliers. The proposed compressor features eliminated glitch at the output …
[PDF][PDF] DESIGN AND ANALYSIS OF 16-BIT VEDIC MULTIPLICATION USING COMPRESSOR ADDERS
M DASARI - 2021 - ece.anits.edu.in
ABSTRACT A novel architecture of Vedic multiplier with‗ Urdhava-tiryakbhyam
'methodology for 16-bit multiplier and multiplicand is proposed with the use of compressor …
'methodology for 16-bit multiplier and multiplicand is proposed with the use of compressor …
[PDF][PDF] FPGA Implementation of Canonical Signed Digit Algorithm Based Floating Point Multiplication
GS Bhavani - 2020 - ece.anits.edu.in
FPGA Implementation of Canonical Signed Digit Algorithm Based Floating Point Multiplication
Page 1 I FPGA Implementation of Canonical Signed Digit Algorithm Based Floating Point …
Page 1 I FPGA Implementation of Canonical Signed Digit Algorithm Based Floating Point …