High performance FPGA based secured hardware model for IoT devices
Data transmission is always vulnerable to assault on the digital side. Cipher strength
analysis is a crucial component of a business or academic safety evaluation. For data …
analysis is a crucial component of a business or academic safety evaluation. For data …
Watermarking and cryptography based image authentication on reconfigurable platform
Now-a-days, multimedia based applications have been developed rapidly. Digital
information is easy to process but it allows illegal users to access the data. For protecting the …
information is easy to process but it allows illegal users to access the data. For protecting the …
FPGA based fast and high-throughput 2-slow retiming 128-bit AES encryption algorithm
This paper presents a high throughput digital design of the 128-bit Advanced Encryption
Standard (AES) algorithm based on the 2-slow retiming technique on FPGA. The C-slow …
Standard (AES) algorithm based on the 2-slow retiming technique on FPGA. The C-slow …
[PDF][PDF] High speed area efficient FPGA implementation of AES algorithm
Now a day digital information is very easy to process, but it allows unauthorized users to
access this information. To protect this information from unauthorized access, Advanced …
access this information. To protect this information from unauthorized access, Advanced …
Design and implementation of advanced encryption standard algorithm on 7th series field programmable gate array
Transmission of data digitally is always susceptible to attacks. Analysis of cipher strength is
a necessary part of the protection assessment of either corporate or academic institutions …
a necessary part of the protection assessment of either corporate or academic institutions …
High-Speed area-efficient implementation of AES algorithm on reconfigurable platform
Nowadays, digital information is very easy to process, but it allows unauthorized users to
access to this information. To protect this information from unauthorized access …
access to this information. To protect this information from unauthorized access …
Efficient hardware architectures for AES on FPGA
N Iyer, PV Anandmohan, DV Poornaiah… - International Conference …, 2011 - Springer
This paper presents design, implementation and comparison of highly efficient architectures
for AES on FPGAS: Iterative architecture and pipelined architecture. The first design is …
for AES on FPGAS: Iterative architecture and pipelined architecture. The first design is …
High performance hardware implementation of AES using minimal resources
PS Abhijith, M Srivastava, A Mishra… - … Systems and Signal …, 2013 - ieeexplore.ieee.org
Increasing need of data protection in computer networks led to the development of several
cryptographic algorithms hence sending data securely over a transmission link is critically …
cryptographic algorithms hence sending data securely over a transmission link is critically …
[PDF][PDF] FPGA based a new low power and self-timed AES 128-bit encryption algorithm for encryption audio signal
Advanced Encryption Standard (AES) algorithm based on a novel asynchronous self-timed
architecture for encryption of audio signals. An asynchronous system is defined as one …
architecture for encryption of audio signals. An asynchronous system is defined as one …
Design of AES architecture with area and speed tradeoff
N Shaji, PL Bonifus - Procedia Technology, 2016 - Elsevier
AES, is the well-accepted cryptographic algorithm which could be utilized to ensure security
of electronic information since it is proven to be resistive to most of the attacks. In this work …
of electronic information since it is proven to be resistive to most of the attacks. In this work …