Method and system for modeling logical circuit blocks including transistor gate capacitance loading effects
BL Dorfman, TE Rosser, JP Soreff - US Patent 7,552,040, 2009 - Google Patents
US7552040B2 - Method and system for modeling logical circuit blocks including transistor gate
capacitance loading effects - Google Patents US7552040B2 - Method and system for modeling …
capacitance loading effects - Google Patents US7552040B2 - Method and system for modeling …
Method and apparatus of simulating a semiconductor integrated circuit at gate level
TY Kim, SY Jang, HS Song - US Patent App. 11/776,174, 2008 - Google Patents
An exemplary embodiment of the present inven tion provides a method for simulating a
semiconductor integrated (IC) at gate level. The method includes providing a net list …
semiconductor integrated (IC) at gate level. The method includes providing a net list …
Method for detecting hazardous high impedance nets
J Grabinski - US Patent 11,275,879, 2022 - Google Patents
METHOD FOR DETECTING HAZARDOUS networks with improved efficiency and accuracy.
According HIGH IMPEDANCE NETS to an aspect, a simulation method for detecting a high …
According HIGH IMPEDANCE NETS to an aspect, a simulation method for detecting a high …
Techniques for calculating circuit block delay and transition times including transistor gate capacitance loading effects
BL Dorfman, TE Rosser, JP Soreff - US Patent App. 12/055,852, 2008 - Google Patents
Techniques for modeling delay and transition times of logical circuit blocks including
transistor gate capacitance loading effects provides improved simulation of logical circuit …
transistor gate capacitance loading effects provides improved simulation of logical circuit …