Recent advances in strain-induced piezoelectric and piezoresistive effect-engineered 2D semiconductors for adaptive electronics and optoelectronics
The development of two-dimensional (2D) semiconductors has attracted widespread
attentions in the scientific community and industry due to their ultra-thin thickness, unique …
attentions in the scientific community and industry due to their ultra-thin thickness, unique …
Si/SiGe heterostructures: from material and physics to devices and circuits
DJ Paul - Semiconductor science and technology, 2004 - iopscience.iop.org
Silicon germanium (SiGe) has moved from being a research material to accounting for a
small but significant percentage of manufactured semiconductor devices. This percentage is …
small but significant percentage of manufactured semiconductor devices. This percentage is …
Semiconductor piezoresistance for microsystems
AA Barlian, WT Park, JR Mallon… - Proceedings of the …, 2009 - ieeexplore.ieee.org
Piezoresistive sensors are among the earliest micromachined silicon devices. The need for
smaller, less expensive, higher performance sensors helped drive early micromachining …
smaller, less expensive, higher performance sensors helped drive early micromachining …
Novel attributes of a dual material gate nanoscale tunnel field-effect transistor
In this paper, we propose the application of a dual material gate (DMG) in a tunnel field-
effect transistor (TFET) to simultaneously optimize the on-current, the off-current, and the …
effect transistor (TFET) to simultaneously optimize the on-current, the off-current, and the …
A 90nm high volume manufacturing logic technology featuring novel 45nm gate length strained silicon CMOS transistors
This paper describes the details of a novel strained transistor architecture which is
incorporated into a 90nm logic technology on 300mm wafers. The unique strained PMOS …
incorporated into a 90nm logic technology on 300mm wafers. The unique strained PMOS …
A 90-nm logic technology featuring strained-silicon
SE Thompson, M Armstrong, C Auth… - … on electron devices, 2004 - ieeexplore.ieee.org
A leading-edge 90-nm technology with 1.2-nm physical gate oxide, 45-nm gate length,
strained silicon, NiSi, seven layers of Cu interconnects, and low-/spl kappa/CDO for high …
strained silicon, NiSi, seven layers of Cu interconnects, and low-/spl kappa/CDO for high …
[图书][B] Fundamentals of tunnel field-effect transistors
During the last decade, there has been a great deal of interest in TFETs. To the best authors'
knowledge, no book on TFETs currently exists. The proposed book provides readers with …
knowledge, no book on TFETs currently exists. The proposed book provides readers with …
The end of CMOS scaling: toward the introduction of new materials and structural changes to improve MOSFET performance
T Skotnicki, JA Hutchby, TJ King… - IEEE Circuits and …, 2005 - ieeexplore.ieee.org
The rapid cadence of metal-oxide semiconductor field-effect transistor (MOSFET) scaling, as
seen in the new 2003 International Technology Roadmap for Semiconductors ITRS), is …
seen in the new 2003 International Technology Roadmap for Semiconductors ITRS), is …
Silicon CMOS devices beyond scaling
W Haensch, EJ Nowak, RH Dennard… - IBM Journal of …, 2006 - ieeexplore.ieee.org
To a large extent, scaling was not seriously challenged in the past. However, a closer look
reveals that early signs of scaling limits were seen in high-performance devices in recent …
reveals that early signs of scaling limits were seen in high-performance devices in recent …
Silicon device scaling to the sub-10-nm regime
In the next decade, advances in complementary metal-oxide semiconductor fabrication will
lead to devices with gate lengths (the region in the device that switches the current flow on …
lead to devices with gate lengths (the region in the device that switches the current flow on …