A large number of interconnections required to implement a binary logic-based circuit leads
to an increase in power/energy consumption and area overhead. Utilizing multiple-valued …

The huge quantity of nodes and interconnections in modern binary circuits leads to
extremely high levels of energy consumption. The interconnection complexity and other …

Multi-valued logic (MVL) has more than two-valued logic to decrease the interconnections
and energy consumption. Also, the market has seen a significant increase in portable …

This paper presents a novel design of ternary circuits using carbon nano-tube transistors
(CNTFETs). Using multi-valued logic can reduce chip interconnections, which can have a …

Using multi-valued logic can lead to reducing the interconnections in the chip. Reducing the
interconnection, in turn, leads to decreasing the chip area and interconnections power …

Using the multi-valued logic causes the reduction in interconnections, thereby leading to the
reduction in chip area and interconnection power dissipation. In order to take advantage of …

This paper presents a novel ultra-low power yet high-performance device and circuit design
paradigm for implementing ternary logic based circuits using Gate-Overlap Tunnel FETs …

It is shown that algebraic fields and rings can become a very promising tool for digital signal
processing. This is mainly due to the fact that any digital signals change in a finite range of …

Delay optimization has now emerged as an important optimization goal in logic synthesis.
The delay optimization for ternary fixed polarity Reed–Muller (FPRM) circuits aims to find a …

Abstract Binary (base-2) comparators suffer from interconnect-complexity and associated
power-delay, area, fan-in/out, reliability and parasitic-overhead. Ternary (base-3) …