In this paper, the Test Pattern Generation (TPG) with a new simple hybrid (dynamic and
static) compaction technique for combinational logic circuits and systems is presented …

Assertions are now widely used in verification as a means to help convey designer intent
and also to simplify the detection of erroneous conditions by the firing of assertions. With this …

Early design space exploration is a practice for avoiding issues that manifest themselves at
late design phases. Nevertheless, the test development has traditionally been postponed to …

Assertions are now widely used in verification as a means to help convey designer intent (as
specification snippets) and also to simplify the detection of erroneous conditions by the firing …

Functional validation is a major bottleneck in microprocessor design methodology.
Simulation is the widely used method for functional validation using billions of random and …

When a pool of functional test sequences is created for simulation-based verification of a
design, the same sequences can be used as manufacturing tests to complement scan …

SRAM-based FPGA covers nearly 60% of the applications, also susceptible to Single Event
Upsets (SEUs) due to radiation. Therefore, FPGA-based systems need to be tested and …

The goal of static test compaction is to reduce the number or tests, or the lengths of test
sequences, without reducing the fault coverage. Static test compaction that reduces the …

This paper describes a new model for a set of test sequences where a set S is described by
a single functional test sequence T. Using this model, a procedure that compacts T compacts …

Recently, the density and intricacy of Very Large-Scale Integration (VLSI) circuits are grown,
and the number of test vectors has increased drastically. Owing to this, the cost of testing is a …