[HTML][HTML] A 32-Bit DSP Instruction Pipeline Control Unit Verification Method Based on Instruction Reordering Strategy

H Wang, S Liu, L Zhang - Symmetry, 2022 - mdpi.com
The growing complexity and size of integrated circuits has made functional verification a
huge challenge. As the control center of integrated circuit hardware design, any design …

Speed-Up in Test Methods Using Probabilistic Merit Indicators

M Fooladi, A Kamran - Journal of Electronic Testing, 2020 - Springer
Deterministic test generation methods are time consuming and, this has led to emergence of
simulation-based approaches. The basis of simulation-based methods is to propose a …

Automated Formal Equivalence Verification of Pipelined Nested Loops in Datapath Designs

P Behnam, B Alizadeh, S Taheri - arXiv preprint arXiv:1712.09818, 2017 - arxiv.org
In this paper, we present an efficient formal approach to check the equivalence of
synthesized RTL against the high-level specification in the presence of pipelining …

Machine-learning assisted model-implemented fault injection

M Moradi, J Denil - … 2020: proceedings of the 8th SEDES …, 2021 - repository.uantwerpen.be
Validation and verification of modern safety-critical systems demand an increasing amount
of time and effort as systems become more complicated. Fault Injection (FI) is a well-known …

Observability-aware post-silicon test generation

F Farahmandi, P Mishra - Post-Silicon Validation and Debug, 2019 - Springer
Simulation is the most widely used form of validation using billions of random and pseudo-
random tests in the traditional design flow. A critical problem in post-silicon debug is to …

SAT-based Silicon Debug of Electrical Errors under Restricted Observability Enhancement

B Kumar, M Fujita, V Singh - Journal of Electronic Testing, 2019 - Springer
Silicon debugging of integrated circuits is exacerbated by the lack of golden responses,
highly restricted observability and irreproducible nature of bugs. Debug engineers need to …

[PDF][PDF] Effective Techniques for Post-silicon Validation and Debug

B Kumar - 2020 - ee.iitb.ac.in
Due to tremendous growth in the complexity of modern designs, bugs inevitably escape the
pre-silicon verification stage because of incomplete functional verification. Furthermore …

Learning Enhanced Diagnosis of Logic Circuit Failures

S Mittal - 2020 - search.proquest.com
As semiconductor manufacturing progresses to smaller process nodes, it is becoming
increasingly difficult to climb the yield learning curve rapidly. The rate of yield learning …

[PDF][PDF] Design Error Diagnosis and Correction of Digital Systems

P Behnam - researchgate.net
Verification is the procedure to check if there is a discrepancy between a design and its
specification. Debugging target is to find the location of the observed error (s). Correction …