Methods of forming a gate structure on a vertical transistor device
JH Zhang, SJ Bentley, KY Lim - US Patent 9,799,751, 2017 - Google Patents
US9799751B1 - Methods of forming a gate structure on a vertical transistor device - Google
Patents US9799751B1 - Methods of forming a gate structure on a vertical transistor device …
Patents US9799751B1 - Methods of forming a gate structure on a vertical transistor device …
Methods of forming vertical transistor devices with different effective gate lengths
R Xie, CC Yeh, T Yamashita, K Cheng - US Patent 9,935,018, 2018 - Google Patents
One illustrative method disclosed herein includes, among other things, forming first and
second vertically-oriented channel (VOC) semiconductor structures for, respectively, first and …
second vertically-oriented channel (VOC) semiconductor structures for, respectively, first and …
Uniform bottom spacers in vertical field effect transistors
(57) ABSTRACT A method for forming a semiconductor device includes forming a
semiconductor fin over a surface of a substrate and forming sacrificial spacers on first and …
semiconductor fin over a surface of a substrate and forming sacrificial spacers on first and …
Replacement metal gate processes for vertical transport field-effect transistor
2018-01-05 Assigned to INTERNATIONAL BUSINESS MACHINES CORPORATION
reassignment INTERNATIONAL BUSINESS MACHINES CORPORATION ASSIGNMENT OF …
reassignment INTERNATIONAL BUSINESS MACHINES CORPORATION ASSIGNMENT OF …
Air gap adjacent a bottom source/drain region of vertical transistor device
R Xie, CC Yeh, K Cheng, T Yamashita - US Patent 10,014,370, 2018 - Google Patents
One illustrative method disclosed herein includes, among other things, forming an initial
bottom spacer above a semiconductor substrate and adjacent a vertically-oriented channel …
bottom spacer above a semiconductor substrate and adjacent a vertically-oriented channel …
Vertical FET with self-aligned source/drain regions and gate length based on channel epitaxial growth process
S Bentley, PH Suvarna, J Frougier… - US Patent 10,236,379, 2019 - Google Patents
(57) ABSTRACT A fin extends from, and is perpendicular to, a planar surface of a substrate.
A self-aligned bottom source/drain conductor is on the substrate adjacent the fin, a bottom …
A self-aligned bottom source/drain conductor is on the substrate adjacent the fin, a bottom …
Vertical gate-all-around transistor with top and bottom source/drain epitaxy on a replacement nanowire, and method of manufacturing the same
E Leobandung - US Patent 10,014,372, 2018 - Google Patents
After providing a Group IV semiconductor nanowire on a substrate, a sacrificial material
portion is formed on sidewalls of a bottom portion of the Group IV semiconductor nanowire …
portion is formed on sidewalls of a bottom portion of the Group IV semiconductor nanowire …
Method and structure for forming a vertical field-effect transistor using a replacement metal gate process
(57) ABSTRACT A method for manufacturing a vertical transistor device includes forming a
first plurality of fins in a first device region on a substrate, and forming a second plurality of …
first plurality of fins in a first device region on a substrate, and forming a second plurality of …
Asymmetric vertical device
E Leobandung - US Patent 10,361,300, 2019 - Google Patents
(52)(57) ABSTRACT A vertical FET with asymmetrically positioned source region and drain
region is provided. The source region of the vertical FET is separated from a gate electrode …
region is provided. The source region of the vertical FET is separated from a gate electrode …
Vertical FET transistor with reduced source/drain contact resistance
A method is presented for reducing contact resistance and parasitic capacitance. The
method includes forming a plu rality of fins over a semiconductor substrate, forming a bottom …
method includes forming a plu rality of fins over a semiconductor substrate, forming a bottom …