A new family of high. performance parallel decimal multipliers

A Vázquez, E Antelo… - 18th IEEE Symposium on …, 2007 - ieeexplore.ieee.org
This paper introduces two novel architectures for parallel decimal multipliers. Our multipliers
are based on a new algorithm for decimal carry-save multioperand addition that uses a …

Improved design of high-performance parallel decimal multipliers

A Vazquez, E Antelo… - IEEE Transactions on …, 2009 - ieeexplore.ieee.org
The new generation of high-performance decimal floating-point units (DFUs) is demanding
efficient implementations of parallel decimal multipliers. In this paper, we describe the …

A radix-10 combinational multiplier

T Lang, A Nannarelli - 2006 Fortieth Asilomar Conference on …, 2006 - ieeexplore.ieee.org
In this work, we present a combinational decimal multiply unit which can be pipelined to
reach the desired throughput. With respect to previous implementations of decimal …

Improving the speed of parallel decimal multiplication

G Jaberipur, A Kaivani - IEEE Transactions on Computers, 2009 - ieeexplore.ieee.org
Hardware support for decimal computer arithmetic is regaining popularity. One reason is the
recent growth of decimal computations in commercial, scientific, financial, and Internet …

Binary-coded decimal digit multipliers

G Jaberipur, A Kaivani - IET Computers & Digital Techniques, 2007 - IET
With the growing popularity of decimal computer arithmetic in scientific, commercial,
financial and Internet-based applications, hardware realisation of decimal arithmetic …

High-speed parallel decimal multiplication with redundant internal encodings

L Han, SB Ko - IEEE Transactions on Computers, 2012 - ieeexplore.ieee.org
The decimal multiplication is one of the most important decimal arithmetic operations which
have a growing demand in the area of commercial, financial, and scientific computing. In this …

The IBM zEnterprise-196 decimal floating-point accelerator

S Carlough, A Collura, S Mueller… - 2011 IEEE 20th …, 2011 - ieeexplore.ieee.org
Decimal floating-point Arithmetic is widely used in commercial computing applications, such
as financial transactions, where rounding errors prevent the use of binary floating-point …

A radix-10 digit-recurrence division unit: algorithm and architecture

T Lang, A Nannarelli - IEEE Transactions on Computers, 2007 - ieeexplore.ieee.org
In this work, we present a radix-10 division unit that is based on the digit-recurrence
algorithm. The previous decimal division designs do not include recent developments in the …

A decimal floating-point specification

MF Cowlishaw, EM Schwarz, RM Smith… - … IEEE Symposium on …, 2001 - ieeexplore.ieee.org
Even though decimal arithmetic is pervasive in financial and commercial transactions,
computers are still implementing almost all arithmetic calculations using binary arithmetic …

A fully redundant decimal adder and its application in parallel decimal multipliers

S Gorgin, G Jaberipur - Microelectronics Journal, 2009 - Elsevier
Decimal hardware arithmetic units have recently regained popularity, as there is now a high
demand for high performance decimal arithmetic. We propose a novel method for carry-free …