Semiconductor device for testing large number of devices and composing method and test method thereof
Provided is a method for testing a plurality of transistors of a semiconductor device. The
method includes forming a plurality of elements or a plurality of logic using a Front End Of …
method includes forming a plurality of elements or a plurality of logic using a Front End Of …
High speed time-interleaved ADC gain offset and skew mitigation
GD Parnaby, V Parthasarathy, JS Wang - US Patent 9,270,291, 2016 - Google Patents
Methods and apparatuses are described for timing skew miti gation in time-interleaved
ADCs (TI-ADCs) that may be per formed for any receive signal without any special signals …
ADCs (TI-ADCs) that may be per formed for any receive signal without any special signals …
Circuit for and method of implementing a time-interleaved analog-to-digital converter
J Shin, H Hedayati - US Patent 9,503,115, 2016 - Google Patents
H03M I/2(2006.01) H03M I/08(2006.01)(57) ABSTRACT H03M I/00(2006.01) A circuit for
implementing a time-interleaved analog-to (52) US Cl. digital converter is described. The …
implementing a time-interleaved analog-to (52) US Cl. digital converter is described. The …
Semiconductor devices and methods for manufacturing the same
According to example embodiments, a semiconductor device and a method for
manufacturing the same are pro vided, the semiconductor device includes a Substrate …
manufacturing the same are pro vided, the semiconductor device includes a Substrate …
Method of designing layout of semiconductor device
K Jeong - US Patent 9,811,626, 2017 - Google Patents
A method of designing a layout of a semiconductor device includes receiving information on
a size of a target chip and a unit placement width for forming a gate line through a self-align …
a size of a target chip and a unit placement width for forming a gate line through a self-align …
Semiconductor having cross coupled structure and layout verification method thereof
324/762. 01 6, 532, 579 B2 3/2003 Sato et al. 6, 662, 350 B2 12/2003 Fried et al. 7, 102, 413
B2. 9/2006 Kuroda 7, 547, 597 B2. 6/2009 Kau et al. 7, 685, 540 B1 3/2010 Madden et al. 7 …
B2. 9/2006 Kuroda 7, 547, 597 B2. 6/2009 Kau et al. 7, 685, 540 B1 3/2010 Madden et al. 7 …
ADC reconfiguration for different data rates
D Xu - US Patent 10,720,936, 2020 - Google Patents
A receiver having analog-to-digital converters (ADC) is disclosed. The ADCs may be
reconfigured based on the data rate of the receiver. For example, more portions of each time …
reconfigured based on the data rate of the receiver. For example, more portions of each time …
Linear feedback shift register-based clock signal generator, time domain-interleaved analog to digital converter and methods
SE Mikes, HC Cranford Jr, JK Koehler… - US Patent …, 2019 - Google Patents
Disclosed is a linear feedback shift register (LFSR)-based clock signal generator that
includes an LFSR, which outputs multi-bit states based on a system clock signal (CLK0) …
includes an LFSR, which outputs multi-bit states based on a system clock signal (CLK0) …
ADC reconfiguration for different data rates
D Xu - US Patent 10,931,295, 2021 - Google Patents
(57) ABSTRACT A receiver having analog-to-digital converters (ADC) is disclosed. The
ADCs may be reconfigured based on the data rate of the receiver. For example, more …
ADCs may be reconfigured based on the data rate of the receiver. For example, more …
ADC slicer reconfiguration for different channel insertion loss
D Xu - US Patent 11,115,040, 2021 - Google Patents
A receiver having analog-to-digital converters (ADC) is disclosed. The ADCs may be
reconfigured based on the insertion loss mode of the receiver. For example, different …
reconfigured based on the insertion loss mode of the receiver. For example, different …