The main goal of the paper is to present a logic synthesis strategy dedicated to an LUT-
based FPGA. New elements of the proposed synthesis strategy include: an original method …

The paper presents a synthesis strategy oriented to the implementation of multi-output
functions into LUT-based FPGA. The key elements of the proposed method include the …

This paper proposes a novel algorithm that, given a data-flow graph and an input/output
constraint, enumerates all convex subgraphs under the given constraint in polynomial time …

Assurance has been defined as" the degree of confidence that security needs are satisfied".
The problem with this definition is that, unless one has a way to specify security needs in …

This article presents a synthesis strategy aimed at minimizing the dynamic power
consumption of combinational circuits mapped in LUT blocks of FPGAs. The implemented …

The paper presents the methods of searching for non-disjoint decomposition using BDD.
Non-disjoint decomposition is a generalization of a classic decomposition model. Its main …

This paper addresses the problem of non-disjoint decomposition of multiple-valued
functions. First, we show that the problem of computing non-disjoint decompositions of a …

Graph dominators provide a general mechanism for identifying re-converging paths in
circuits. This is useful in a number of CAD applications, including computation of signal …

Most of the logic synthesis algorithms are not scalable for large networks and, for this
reason, partitioning is often applied. However traditional mincut-based partitioning …

In this paper we present a fast algorithm for computing common multiple-vertex dominators
in circuit graphs. Dominators are widely used in CAD applications such as satisfiability …