Fault tolerant reconfigurable hardware design using BIST on SRAM: A review
AKS Pundir, OP Sharma - 2017 International Conference on …, 2017 - ieeexplore.ieee.org
This Paper presents an exhaustive review on BIST technique used in different fault tolerant
systems and also consider the fault detection methodologies used in these systems. BIST is …
systems and also consider the fault detection methodologies used in these systems. BIST is …
Master-slave based test cost reduction method for DNN accelerators
US Solangi, M Ibtesam, S Park - IEICE Electronics Express, 2021 - jstage.jst.go.jp
To achieve reduction in test time of accelerators, broadcasting of test patterns is used for
simultaneous testing of processing elements (PEs). However, number of PEs tested …
simultaneous testing of processing elements (PEs). However, number of PEs tested …
Time multiplexed LBIST for in-field testing of automotive AI accelerators
US Solangi, M Ibtesam, S Park - IEICE Electronics Express, 2021 - jstage.jst.go.jp
Logic BIST is a safety mechanism, which performs testing for Automotive electronics.
However, pseudorandom LBIST patterns results in increased test time and test power. In this …
However, pseudorandom LBIST patterns results in increased test time and test power. In this …
[PDF][PDF] Test Modules Design for a SerDes Chip in 130 nm CMOS technology
CF Limones-Mora - 2016 - core.ac.uk
Test Modules Design for a SerDes Chip in 130 nm CMOS technology Page 1 Instituto Tecnológico
y de Estudios Superiores de Occidente 2016-07 Test Modules Design for a SerDes Chip in 130 nm …
y de Estudios Superiores de Occidente 2016-07 Test Modules Design for a SerDes Chip in 130 nm …