Low-power CMOS digital design

AP Chandrakasan, S Sheng… - IEICE Transactions on …, 1992 - search.ieice.org
Motivated by emerging battery-operated applications that demand intensive computation in
portable environments, techniques are investigated which reduce power consumption in …

Minimizing power consumption in digital CMOS circuits

AP Chandrakasan, RW Brodersen - Proceedings of the IEEE, 1995 - ieeexplore.ieee.org
An approach is presented for minimizing power consumption for digital systems
implemented in CMOS which involves optimization at all levels of the design. This …

A portable multimedia terminal

S Sheng, A Chandrakasan… - IEEE Communications …, 1992 - ieeexplore.ieee.org
A personal communications system (PCS) that centers on integration of services to provide
access to data and communications using a specialized, wireless multimedia terminal is …

Low-power design of memory intensive functions

DB Lidsky, JM Rabaey - … of 1994 IEEE Symposium on Low …, 1994 - ieeexplore.ieee.org
Much of the recent efforts into low power design techniques neglects the impact memory
accesses have on power consumption. This paper provides a summary of the techniques …

An integrated circuit design for pruned tree-search vector quantization encoding with an off-chip controller

R Jain, A Madisetti, RL Baker - IEEE Transactions on circuits …, 1992 - ieeexplore.ieee.org
The design of an encoder for pruned tree-search vector quantization (VQ) is discussed. This
allows near-optimal performance in a mean square error sense while keeping the hardware …

Low power design of memory intensive functions. Case study: vector quantization

DB Lidsky, JM Rabaey - … of 1994 IEEE Workshop on VLSI …, 1994 - ieeexplore.ieee.org
This paper demonstrates techniques to optimize power consumption of memory intensive
applications. A design example-a video, vector quantizer encoder-demonstrates how …

VLSI systolic binary tree-searched vector quantizer for image compression

WC Fang, CY Chang, BJ Sheu… - … Transactions on Very …, 1994 - ieeexplore.ieee.org
A high-speed image compression VLSI processor based on the systolic architecture of
difference-codebook binary tree-searched vector quantization has been developed to meet …

Algorithm and architectural level methodologies for low power

R Mehra, DB Lidsky, A Abnous, PE Landman… - Low Power Design …, 1996 - Springer
With ever increasing integration levels, power has become a critical design parameter.
Consequently, a lot of effort has gone into achieving lower dissipation at all levels of the …

Single chip design for fast image compression

VK Prasanna, CL Wang, H Park - US Patent 5,468,069, 1995 - Google Patents
Video data compression techniques reduce necessary stor age size and communication
channel bandwidth while main taining acceptable fidelity. Vector quantization provides bet …

VLSI implementation of a tree searched vector quantizer

RK Kolagotla, SS Yu, JF JaJa - IEEE transactions on signal …, 1993 - ieeexplore.ieee.org
The VLSI design and implementation of a tree-searched vector quantizer is presented. The
number of processors needed is equal to the depth of the tree. All processors are identical …