Leaky way: a conflict-based cache covert channel bypassing set associativity

Y Guo, X Xin, Y Zhang, J Yang - 2022 55th IEEE/ACM …, 2022 - ieeexplore.ieee.org
Modern * 86 processors feature many prefetch instructions that developers can use to
enhance performance. However, with some prefetch instructions, users can more directly …

Autocat: Reinforcement learning for automated exploration of cache-timing attacks

M Luo, W Xiong, G Lee, Y Li, X Yang… - … Symposium on High …, 2023 - ieeexplore.ieee.org
The aggressive performance optimizations in modern microprocessors can result in security
vulnerabilities. For example, timing-based attacks in processor caches can steal secret keys …

DAGguise: mitigating memory timing side channels

PW Deutsch, Y Yang, T Bourgeat, J Drean… - Proceedings of the 27th …, 2022 - dl.acm.org
This paper studies the mitigation of memory timing side channels, where attackers utilize
contention within DRAM controllers to infer a victim's secrets. Already practical, this class of …

Cachefx: A framework for evaluating cache security

D Genkin, W Kosasih, F Liu, A Trikalinou… - Proceedings of the …, 2023 - dl.acm.org
Over the last two decades, the danger of sharing resources between programs has been
repeatedly highlighted. Multiple side-channel attacks, which seek to exploit shared …

Towards a metrics suite for evaluating cache side-channel vulnerability: Case studies on an open-source RISC-V processor

P Guo, Y Yan, J Wang, J Zhong, Y Liu, J Xu - Computers & Security, 2023 - Elsevier
Caches are key microarchitectural components of modern processors to improve memory
access speed. However, attackers can readily implement timing side-channel attacks by …

Ivcache: Defending cache side channel attacks via invisible accesses

Y Guo, A Zigerelli, Y Zhang, J Yang - Proceedings of the 2021 on Great …, 2021 - dl.acm.org
The sharing of last-level cache (LLC) among different CPU cores makes cache vulnerable to
side channel attacks. An attacker can get private information about co-running applications …

Evaluation of cache attacks on arm processors and secure caches

S Deng, N Matyunin, W Xiong… - IEEE Transactions …, 2021 - ieeexplore.ieee.org
Timing-based side and covert channels in processor caches continue to be a threat to
modern computers. This work shows for the first time, a systematic, large-scale analysis of …

RECAST: Mitigating Conflict-Based Cache Attacks Through Fine-Grained Dynamic Mapping

X Zhang, H Gong, R Chang… - IEEE Transactions on …, 2024 - ieeexplore.ieee.org
Conflict-based cache attacks can leak critical information from target programs. Accordingly,
randomization-based cache designs have emerged as an efficient and LLC-favorable way …

One more set: Mitigating conflict-based cache side-channel attacks by extending cache set

Y Gu, M Tang, Q Wang, H Wang, H Ding - Journal of Systems Architecture, 2023 - Elsevier
Caches are vulnerable to side-channel attacks as a type of shared hardware resource. Most
existing defense methods can be categorized into two categories: partition and …

PREDATOR: A Cache Side-Channel Attack Detector Based on Precise Event Monitoring

M Wu, S McCamant, PC Yew… - 2022 IEEE International …, 2022 - ieeexplore.ieee.org
Recent work has demonstrated the security risk associated with micro-architecture side-
channels. The cache timing side-channel is a particularly popular target due to its availability …