Latchup immunity is a challenging issue for the design of power supply clamps used in high-
voltage electrostatic discharge (ESD) protection applications. While silicon-controlled …

This paper discusses challenges and solutions of automotive ESD protection design in a
reliability driven industry. Various ESD/EMI specifications are compared, which impact the …

For high-voltage (HV) applications, the electrostatic discharge (ESD) protection design using
a traditional HV device, such as laterally diffused MOSFETs, usually consumes large silicon …

A new high voltage lateral PNP with sufficient current density for small footprint ESD
protection is experimentally demonstrated in a 40 V drain-extended CMOS process. It is …

The nonuniform current distribution of high-voltage laterally-diffused metal-oxide
semiconductor (HV LDMOS) is an inevitable phenomenon if the process does not consider …

We demonstrate a PNP electrostatic discharge (ESD) protection device with adjustable
trigger and holding voltage, proposed and verified in a 0.18-BCD process for 8–65-V …

The low snapback holding voltage of the SCR-LDMOS device makes it susceptible to latch-
up failure, when used in power-rail ESD (electro-static discharge) clamp circuits. In order to …

Transient voltage overshoots of a high voltage (20 V) ESD clamp based on bipolar
transistors in a smart power technology are studied using different TLP pulse conditions (rise …

In this paper, ESD triggering mechanism of the parasitic PNP bipolar transistor in rail-based
ESD protection circuits was investigated. The device simulation results show that the …

This work investigates design options for three different classes of high voltage lateral ESD
PNPs in a 0.5-µm BCD technology. The PNP layout topology is observed to affect the area …