A low power single bit-line configuration dependent 7T SRAM bit cell with process-variation-tolerant enhanced read performance

B Rawat, P Mittal - Analog Integrated Circuits and Signal Processing, 2023 - Springer
Cache memory is a key component for most microprocessors in embedded system. The
increasing processing load has resulted in an upsurge in the demand for low power, high …

Design and analysis of SRAM cell using swing restoration inverter for low power applications

RM Rawat, V Kumar - International Journal of Electronics, 2025 - Taylor & Francis
ABSTRACT SRAM cells play a crucial role in the design of system-on-chips (SoCs),
constituting a substantial portion of the die area and thereby contributing to increased power …

Design of dual port 9T SRAM cell with parallel processing and high performance computing

Y Chopra, P Mittal - Physica Scripta, 2024 - iopscience.iop.org
To meet industry requirements of higher transistor count SRAM cells this paper is proposing,
a nine-transistor configuration static random access memory (SRAM) cell which is …

Comparative Analysis of Various SRAM Bit Cells for 32 nm Technology Node

P Srivastava, B Rawat, P Mittal - International Conference on Data Science …, 2023 - Springer
The growing demand for low power and faster processers had mandated designing cache
memory that assists the same. Thus, this paper gives a comparison review of different 7T …

Optimized leakage control in CMOS NAND gates: the in-triggering technique

R Arya, BK Singh - Physica Scripta, 2024 - iopscience.iop.org
Leakage power, now the largest contributor to integrated circuit power consumption, is rising
quickly, according to the International Technology Roadmap for Semiconductors (ITRS). As …

A Single Line 8T SRAM Bit Cell with Robust Read, Hold Stability and Low Power

Y Chopra, P Mittal - International Conference on Data Science and …, 2023 - Springer
This article is focussing on the analysis of an eight transistor SRAM bit cell which is
accessed by single bit line. The various analyses, this brief includes, are power …

Secure and Reliable Single-Ended 10T SRAM Cell

A Sharma, SF Naz, AP Shah - 2024 8th IEEE Electron Devices …, 2024 - ieeexplore.ieee.org
Several factors impact Static Random Access Memory performance, notably leakage current
attack-based Side-Channel Attacks (SCA) and half-select issues. High radiation …

[PDF][PDF] Low leakage decoder using dual-threshold technique for static random-access memory applications

R Krishna, P Duraiswamy - Indonesian Journal of Electrical …, 2023 - academia.edu
Decoders are one of the significant peripheral components of static randomaccess memory
(SRAM). As the CMOS technology moves towards nano scale regime, the leakage power …

Simulation Analysis and Performance Comparison for the Memory Cells

SV Kumar - Journal of Electrical and Electronics Engineering, 2021 - search.proquest.com
The designing of the efficient memory cell is mandatory for the today's portable
applications.[...] it is a great challenge to design a static random-access memory (SRAM) cell …

A Comparative Performance Analysis of 10 T and 11 T SRAM Cells

P Yadav, P Mittal - International Conference on Women Researchers in …, 2023 - Springer
Memory is already known to be one of the most crucial parts of any electronic system.
However, a class of memory called the cache memory is even more crucial among the type …