Vertical transistor with uniform bottom spacer formed by selective oxidation
A method of forming a vertical transistor includes forming at least one fin on stacked layers.
The stacked layers include a substrate, a doped silicon layer, and an intrinsic layer …
The stacked layers include a substrate, a doped silicon layer, and an intrinsic layer …
Integrated circuit devices and methods of manufacturing the same
JY Chung, YS Lee, HJ Kim, HS Rhee… - US Patent …, 2017 - Google Patents
An integrated circuit device includes first and second fin type active regions having different
conductive type channel regions, a first device isolation layer covering both sidewalk of the …
conductive type channel regions, a first device isolation layer covering both sidewalk of the …
Semiconductor devices and methods of manufacturing the same
D Kim, S Geo-Myung, DS Shin - US Patent 9,847,224, 2017 - Google Patents
(57) ABSTRACT A semiconductor device includes: a substrate including a plurality of first
active regions and a plurality of second active regions; a plurality of first gate structures …
active regions and a plurality of second active regions; a plurality of first gate structures …
Vertical transport FET devices with uniform bottom spacer
US9799749B1 - Vertical transport FET devices with uniform bottom spacer - Google Patents
US9799749B1 - Vertical transport FET devices with uniform bottom spacer - Google Patents …
US9799749B1 - Vertical transport FET devices with uniform bottom spacer - Google Patents …
Bottom spacer formation for vertical transistor
O Gluschenkov, SC Mehta, S Mochizuki… - US Patent …, 2017 - Google Patents
(57) ABSTRACT A bilayer of silicon dioxide and silicon nitride is formed on exposed
surfaces of at least one semiconductor fin having a bottom source/drain region located at the …
surfaces of at least one semiconductor fin having a bottom source/drain region located at the …
Variable gate lengths for vertical transistors
BA Anderson, EJ Nowak - US Patent 10,026,653, 2018 - Google Patents
The method includes prior to depositing a gate on a first vertical FET on a semiconductor
substrate, depositing a first layer on the first vertical FET on the semiconductor sub strate …
substrate, depositing a first layer on the first vertical FET on the semiconductor sub strate …
Methods, apparatus, and system for improved nanowire/nanosheet spacers
S Bentley, D Nayak - US Patent 10,249,710, 2019 - Google Patents
(57) ABSTRACT A semiconductor structure, comprising a semiconductor substrate; at least
one fin, wherein the at least one fin comprises one or more first layers and one or more …
one fin, wherein the at least one fin comprises one or more first layers and one or more …
Vertical FET devices with multiple channel lengths
HV Mallela, RA Vega, R Venigalla - US Patent 10,424,515, 2019 - Google Patents
(57) ABSTRACT A semiconductor device comprises a first source/drain region arranged on
a semiconductor substrate, a second source/drain region arranged on the semiconductor …
a semiconductor substrate, a second source/drain region arranged on the semiconductor …
Method of forming vertical transistor having dual bottom spacers
O Gluschenkov, SC Mehta, S Mochizuki… - US Patent …, 2018 - Google Patents
A method of forming a spacer for a vertical transistor is provided. The method includes
forming a fin structure on a substrate, depositing a first spacer on exposed surfaces of the …
forming a fin structure on a substrate, depositing a first spacer on exposed surfaces of the …
Vertical field effect transistor (VFET) having a self-aligned gate/gate extension structure and method
H Zang - US Patent 10,068,987, 2018 - Google Patents
Disclosed are embodiments of a semiconductor structure that includes a vertical field effect
transistor (VFET). The VFET has a fin-shaped body that includes a semiconductor fin and an …
transistor (VFET). The VFET has a fin-shaped body that includes a semiconductor fin and an …