Design and analysis of 8-bit ripple Carry Adder using nine Transistor Full Adder

GR Padmini, O Rajesh, K Raghu… - 2021 7th …, 2021 - ieeexplore.ieee.org
This paper uses a nine-transistor full adder model to design an eight-bit ripple carry adder
for less power consumption. The conventional full adder design consists of 28 transistors …

4-2 Compressor design with new XOR-XNOR module

S Kumar, M Kumar - 2014 Fourth International Conference on …, 2014 - ieeexplore.ieee.org
In this paper, a low-power high speed 4-2 compressor circuit is proposed for fast digital
arithmetic integrated circuits. The 4-2 compressor has been widely employed for multiplier …

[PDF][PDF] Area and power efficient CMOS adder design by hybridizing PTL and GDI technique

A Sharma, R Mehra - International Journal of Computer Applications, 2013 - Citeseer
In this paper an area and power efficient 9T adder design has been presented by
hybridizing PTL and GDI techniques. The proposed adder design consist of 5 NMOS and 4 …

Securing End-Node to Gateway Communication in LoRaWAN with a Lightweight Security Protocol

JJ Barriga, SG Yoo - IEEE Access, 2022 - ieeexplore.ieee.org
The arrival of IoT has brought constant innovation. This innovation has allowed many
“things”(sensors, wearable devices, smart appliances, among others) to be connected to the …

A novel ultra low power accuracy configurable adder at transistor level

AM Hassani, M Rezaalipour… - 2018 8th International …, 2018 - ieeexplore.ieee.org
Low power consumption, nowadays, has emerged to be an indispensable factor as there is
a growing demand for designing efficient computation-intensive systems and integrating …

[PDF][PDF] Performance analysis of magnitude comparator using different design techniques

M Aggarwal, R Mehra - International Journal of Computer …, 2015 - researchgate.net
Comparators are a basic design module and element in modern digital VLSI design, digital
signal processors and data processing application-specific integrated circuits. This paper …

Area and power efficient carry select adder using 8T full adder

B Sathyabhama, M Deepika… - … on Communications and …, 2015 - ieeexplore.ieee.org
Carry select adder (CSLA) one of the fastest adders used in complex data processing to
perform fast arithmetic functions. Minimum amount of power consumption is a major driving …

Pass transistor with dual threshold voltage domino logic design using standby switch for reduced subthreshold leakage current

S Yuan, Y Li, Y Yuan, Y Liu - Microelectronics Journal, 2013 - Elsevier
Dual threshold voltages domino design methodology utilizes low threshold voltages for all
transistors that can switch during the evaluate mode and utilizes high threshold voltages for …

[PDF][PDF] Efficient Implementation of 2-Bit Magnitude Comparator Using PTL

S Bhuvaneswari, R Prabakaran… - International Journal of …, 2017 - academia.edu
Nowadays the requirements of low power electronics play a vital role in various fields. In this
paper we introducing the novel comparator is one of the fundamental units in VLSI design …

A novel power efficient N-MOS based 1-bit full adder

D Datta, D Datta - 2016 International Conference on …, 2016 - ieeexplore.ieee.org
A full adder circuit is considered as one of the basic building blocks of Digital Signal
Processors (DSPs), Arithmetic and Logic Units (ALUs), Application Specific Integrated …