A Systematic Review on Distributed Arithmetic-Based Hardware Implementation of Adaptive Digital Filters

S Yergaliyev, MT Akhtar - IEEE Access, 2023 - ieeexplore.ieee.org
Adaptive Digital Filters (ADFs) are computationally demanding Digital Signal Processing
(DSP) systems with applications in diverse areas signal processing, such as active noise …

Two distributed arithmetic based high throughput architectures of non-pipelined LMS adaptive filters

MT Khan, MA Alhartomi, S Alzahrani, RA Shaik… - IEEE …, 2022 - ieeexplore.ieee.org
Distributed arithmetic (DA) is an efficient look-up table (LUT) based approach. The
throughput of DA based implementation is limited by the LUT size. This paper presents two …

Systolic architecture for adaptive block FIR filter for throughput using distributed arithmetic

CP Chowdari, JB Seventline - International Journal of Speech Technology, 2020 - Springer
In this paper, the design of distributed arithmetic (DA) finite impulse response (FIR) filter
using block least mean square algorithm (BLMS) based on systolic array architecture with …

High-performance VLSI architecture of DLMS adaptive filter for fast-convergence and low-MSE

MT Khan, RA Shaik - … Transactions on Circuits and Systems II …, 2022 - ieeexplore.ieee.org
This brief presents a high-performance VLSI architecture of delayed least mean square
(DLMS) adaptive filter for fast-convergence and low-mean square error (MSE) using …

VLSI implementation of distributed arithmetic based block adaptive finite impulse response filter

PC Ch, JB Seventline - Materials Today: Proceedings, 2020 - Elsevier
In this paper, an efficient VLSI architecture of distributed arithmetic (DA) based block least
mean square (BLMS) adaptive finite impulse response (ADFIR) filter implementation with …

Application of Distributed Arithmetic to Adaptive Filtering Algorithms: Trends, Challenges and Future

M Khan - arXiv preprint arXiv:2403.08099, 2024 - arxiv.org
The utilization of distributed arithmetic (DA) in AF algorithms has gained significant attention
in recent years due to its potential to enhance computational efficiency and reduce resource …

Power Optimized VLSI Architecture of Distributed Arithmetic Based Block LMS Adaptive Filter

CK Narayanappa, MN Divya… - … Journal of Electrical …, 2023 - ijeer.forexjournal.co.in
In this paper, we are presenting a power-efficient Distributed Arithmetic (DA) based Block
Least Mean Square (BLMS) Adaptive Digital Filter (ADF). The proposed DA BLMS …

[PDF][PDF] Efficient Hardware Architecture for Taylor-Series Expansion Calculation Using Distributed Arithmetic with Term Division

X Hemthavy, J Wei, S Katayama, A Kuwana… - kobaweb.ei.st.gunma-u.ac.jp
This paper describes the digital arithmetic that reduces the calculation and hardware (logic
circuits and memory) for Taylor series expansion calculation by applying the distributed (bit …

[引用][C] FPGA implementation of efficient VLSI architecture of DLMS adaptive filter algorithm

P Student - Turkish J. Comput. Math. Educ., 2021

[PDF][PDF] 分散型積和演算を用いたテイラー展開省面積演算回路の設計

X Hemthavy - 2024 - gunma-u.repo.nii.ac.jp
集積回路技術の発展により, 電子計算機や携帯電子機器など多岐にわたり高速・高精度・省面積で
あることなどが求められる. それとともに積和演算処理が多く使われるが, 乗算器を用いる個数が …