[图书][B] Closing the gap between ASIC & custom: tools and techniques for high-performance ASIC design

D Chinnery, KW Keutzer - 2002 - books.google.com
This book carefully details design tools and techniques for high-performance ASIC design.
Using these techniques, the performance of ASIC designs can be improved by two to three …

[PDF][PDF] Closing the gap between ASIC and custom: An ASIC perspective

DG Chinnery, K Keutzer - dac, 2000 - Citeseer
We investigate the differences in speed between applicationspecific integrated circuits and
custom integrated circuits when each are implemented in the same process technology, with …

Transistor count reduction by gate merging

CM de Oliveira Conceição… - IEEE Transactions on …, 2019 - ieeexplore.ieee.org
A large set of ASICs uses much more transistors than its necessity, as they use a library of
cells with a limited amount of logic functions. This small number of logic functions in a …

A methodology for transistor-efficient supergate design

D Kagaris, T Haniotakis - IEEE transactions on very large scale …, 2007 - ieeexplore.ieee.org
The number of transistors required for the implementation of a logic function is a
fundamental consideration in digital VLSI design. While the determination of a series …

DAG based library-free technology mapping

FS Marques, LS Rosa Jr, RP Ribas… - Proceedings of the 17th …, 2007 - dl.acm.org
This paper proposes a library-free technology mapping algorithm to reduce delay in
combinational circuits. The algorithm reduces the overall number of series transistors …

Process for automated generation of design-specific complex functional blocks to improve quality of synthesized digital integrated circuits in CMOS using altering …

D Bhattacharya, V Boppana, R Murgai… - US Patent 7,003,738, 2006 - Google Patents
US7003738B2 - Process for automated generation of design-specific complex functional
blocks to improve quality of synthesized digital integrated circuits in CMOS using altering …

Switch level optimization of digital CMOS gate networks

LS da Rosa, FR Schneider, RP Ribas… - 2009 10th International …, 2009 - ieeexplore.ieee.org
This paper presents a comprehensive investigation of how transistor level optimizations can
be used to increase design quality of CMOS logic gate networks. Different properties of …

A knowledge representation system for integration of general and case-specific knowledge

A Aamodt - … Sixth International Conference on Tools with …, 1994 - ieeexplore.ieee.org
Combining various knowledge types-and reasoning methods-in knowledge-based systems
is a challenge to the knowledge representation task. The paper describes an object …

Optimized power-delay curve generation for standard cell ICs

M Vujkovic, C Sechen - Proceedings of the 2002 IEEE/ACM international …, 2002 - dl.acm.org
An effective way to compare logic techniques, logic families, or cell libraries is by means of
power (or area) versus delay plots, since the efficiency of achieving a particular delay is of …

Exact lower bound for the number of switches in series to implement a combinational logic cell

FR Schneider, RP Ribas… - … on Computer Design, 2005 - ieeexplore.ieee.org
This paper addresses the question of how many serial switches are necessary to implement
a given logic function as a switch network. This issue is important because it affects directly …