Adapting magnetoresistive memory devices for accurate and on-chip-training-free in-memory computing
Memristors have emerged as promising devices for enabling efficient multiply-accumulate
(MAC) operations in crossbar arrays, crucial for analog in-memory computing (AiMC) …
(MAC) operations in crossbar arrays, crucial for analog in-memory computing (AiMC) …
Training Neural Networks With In-Memory-Computing Hardware and Multi-Level Radix-4 Inputs
Training Deep Neural Networks (DNNs) requires a large number of operations, among
which matrix-vector multiplies (MVMs), often of high dimensionality, dominate. In-Memory …
which matrix-vector multiplies (MVMs), often of high dimensionality, dominate. In-Memory …
Low-cost 7t-sram compute-in-memory design based on bit-line charge-sharing based analog-to-digital conversion
Although compute-in-memory (CIM) is considered as one of the promising solutions to
overcome memory wall problem, the variations in analog voltage computation and analog-to …
overcome memory wall problem, the variations in analog voltage computation and analog-to …
A Fully Row/Column-Parallel MRAM In-Memory Computing Macro With Memory-Resistance Boosting and Weighted Multi-Column ADC Readout
This work demonstrates a 256 (row) 512 (col.) fully row/column-parallel in-memory
computing (IMC) macro employing foundry MRAM in 22-nm FD-SOI CMOS. Embedded …
computing (IMC) macro employing foundry MRAM in 22-nm FD-SOI CMOS. Embedded …
Enhancing the Accuracy of Resistive In-Memory Architectures using Adaptive Signal Processing
HM Ou, NR Shanbhag - ICASSP 2023-2023 IEEE International …, 2023 - ieeexplore.ieee.org
Analog in-memory computing architectures (IMCs) have exhibited high energy efficiency
over conventional digital architectures. The use of resistive memory arrays such as magnetic …
over conventional digital architectures. The use of resistive memory arrays such as magnetic …
Design space exploration of dense and sparse mapping schemes for RRAM architectures
The impact of device and circuit-level effects in mixed-signal Resistive Random Access
Memory (RRAM) accelerators typically manifest as performance degradation of Deep …
Memory (RRAM) accelerators typically manifest as performance degradation of Deep …
Scalable fully pipelined hardware architecture for in-network aggregated AllReduce communication
The Ring-AllReduce framework is currently the most popular solution to deploy industry-
level distributed machine learning tasks. However, only about half of the maximum …
level distributed machine learning tasks. However, only about half of the maximum …
Analog Multiply-Accumulate Cell With Multi-Bit Resolution for All-Analog AI Inference Accelerators
R Nägele, J Finkbeiner, V Stadtlander… - … on Circuits and …, 2023 - ieeexplore.ieee.org
Mixed-signal AI accelerators offer the possibility of higher energy efficiency for moderate
resolution computations compared to their digital counterparts. All-analog implementations …
resolution computations compared to their digital counterparts. All-analog implementations …
Design of an energy efficient analog two-quadrant multiplier cell operating in weak inversion
R Nägele, J Finkbeiner, M Grözing… - 2022 20th IEEE …, 2022 - ieeexplore.ieee.org
Analog low precision arithmetic circuits offer a significantly higher energy efficiency than
their digital counterparts, which makes them ideally suited for low precision neuromorphic …
their digital counterparts, which makes them ideally suited for low precision neuromorphic …
Proposal of high density two-bits-cell based NAND-like magnetic random access memory
In this brief, we propose a Two-bits-cell based NAND-Like MRAM device. The structure is
composed of several stacking cells sharing the same heavy metal and each cell is …
composed of several stacking cells sharing the same heavy metal and each cell is …