A high linearity pulsewidth control loop (PWCL) is proposed in this paper. Using the linear
control stage (CS) and digital-controlled charge pump (DCCP), the proposed PWCL can be …

A 1.5-V 512-Mb DDR3 synchronous DRAM prototype was designed and fabricated in 80-nm
technology. Critical to the signal integrity in DDR3 point-to-2points (P22P) interfacing is an …

In this paper, delay-locked loops (DLLs) used in dynamic random access memory (DRAM)
are analyzed. DLLs can be categorized into digital-or analog-based topologies. This …

A DLL with a second order duty cycle corrector which consists of a low pass filter and an
integrator is presented. This paper shows the analysis and the design of the second order …

This paper deals with the designing an interface between AXI Protocol based system and
DDR3 Memory. It enables an AXI host to read and write data in a DDR3 Memory. It has been …

This paper describes the implementation of AXI compliant DDR3 memory controller. It
discusses the overall architecture of the DDR3 controller along with the detailed design and …

A 1.6 Gb/s/pin 1Gb DDR3 SDRAM with a CAS latency of 8 at 1.5 V is developed using an 80
nm dual poly CMOS process, which consumes 30 mA of IDD2N and 160 mA of IDD4R. With …

Significant worldwide growth is witnessed in development and deployment of huge numbers
of heterogeneous sensor networks. These all brings the issue of state-of-the-art federations …

A Duty Cycle Corrector (DCC) with wide operation frequency band, wide duty-cycle
correction range, high duty accuracy and low power consumption performance is proposed …

A 1.5 V, 512 Mbit DDR3 synchronous DRAM prototype with 1.6 Gbps/pin was designed in
80nm technology. Output drivers are merged with ODT and are armed with SCR type ESD …