Review of basic classes of dividers based on division algorithm

US Patankar, A Koel - IEEE Access, 2021 - ieeexplore.ieee.org
The electronics world is very well described in two distinct but dependent interdisciplinary
areas, namely hardware and software. Arithmetic operations are very vital building blocks of …

Novel data dependent divider circuit block implementation for complex division and area critical applications

US Patankar, ME Flores, A Koel - Scientific Reports, 2023 - nature.com
This article elaborates on the state-of-the-art novel Udayan S. Patankar (USP)-Awadhoot
algorithm for distinctive implementation area improvement for area-critical electronic …

Constructing high radix quotient digit selection tables for SRT division and square root

Z Liu, X Song, Z Wang, Y Wang… - IEEE Transactions on …, 2023 - ieeexplore.ieee.org
High radix SRT division plays an important role in contemporary microprocessors as the
quotient digit selection tables effectively reduce the computation complexity of the quotient …

Stereo Matching Accelerator With Re-Computation Scheme and Data-Reused Pipeline for Autonomous Vehicles

K Li, X Fang, Y Ma, W Zhang, P Dong… - … on Circuits and …, 2024 - ieeexplore.ieee.org
Binocular stereo vision is a depth estimation technique by imitating human eyes. It is widely
used in various fields, such as self-driving cars, SLAM, and 3D reconstruction. However …

Scalable architecture of constant division on FPGA

D Gorodecky, L Sousa - 2023 IEEE 30th Symposium on …, 2023 - ieeexplore.ieee.org
This paper proposes a method for hardware integer division by a constant, based only on
combinational logic, ie without requiring storage and feedback in calculations. The proposed …

A Low-Latency Divider Design for Embedded Processors

X Wei, Y Yang, J Chen - Sensors, 2022 - mdpi.com
Division is generally regarded as a low-frequency, high-latency operation in integer
operations. Division is also the operation that stalls the processor pipeline most frequently …

An architecture of area-effective high radix floating-point divider with low-power consumption

Y Yang, Q Yuan, J Liu - IEEE Access, 2021 - ieeexplore.ieee.org
In this paper, a novel architecture of area-effective high-radix floating-point divider with low
power consumption is proposed. By extending the principle of the standard SRT algorithm …

Matrix Inversion Accelerated MCU Circuit for Image Recognition Pertinent Computation

W Wang, Y Jin, Q Yuan, H Sun - 2023 International Technical …, 2023 - ieeexplore.ieee.org
As the most complex computation in the fundamental matrix manipulation, the operation of
matrix inversion limits the processing capability in the field of the image recognition and the …

[PDF][PDF] DIGITAL DIVISION ALGORITHMS FOR EFFICIENT EXECUTION ON INTEGRATED CIRCUITS

A Obshta, V Khoma, A Prokopchuk - 2024 - science.lpnu.ua
In this paper, we analyse division algorithms for use on chips and propose the
implementation of an optimal divider for these chips. By “optimal”, we refer to an algorithm …

An Area and Power Efficient Design of Fused integer-floating point unit for RISC-V cores

W Feng, H Chen, G Lin, X He - 2023 3rd International …, 2023 - ieeexplore.ieee.org
With the development of intelligent algorithms and the advent of the Internet of Things era,
the floating-point arithmetic unit has increasingly become an indispensable part of general …