Chi2: Feature selection and discretization of numeric attributes
Discretization can turn numeric attributes into discrete ones. Feature selection can eliminate
some irrelevant attributes. This paper describes Chi2 a simple and general algorithm that …
some irrelevant attributes. This paper describes Chi2 a simple and general algorithm that …
Ibm power6 microarchitecture
HQ Le, WJ Starke, JS Fields… - IBM Journal of …, 2007 - ieeexplore.ieee.org
This paper describes the implementation of the IBM POWER6™ microprocessor, a two-way
simultaneous multithreaded (SMT) dual-core chip whose key features include binary …
simultaneous multithreaded (SMT) dual-core chip whose key features include binary …
Energy-efficient floating-point unit design
S Galal, M Horowitz - IEEE Transactions on computers, 2010 - ieeexplore.ieee.org
Energy-efficient computation is critical if we are going to continue to scale performance in
power-limited systems. For floating-point applications that have large amounts of data …
power-limited systems. For floating-point applications that have large amounts of data …
New flexible multiple-precision multiply-accumulate unit for deep neural network training and inference
In this paper, a new flexible multiple-precision multiply-accumulate (MAC) unit is proposed
for deep neural network training and inference. The proposed MAC unit supports both fixed …
for deep neural network training and inference. The proposed MAC unit supports both fixed …
Fused multiply-add functional unit
S Oberman, MY Siu, DC Tannenbaum - US Patent 8,106,914, 2012 - Google Patents
(57) ABSTRACT A functional unit is added to a graphics processor to provide direct support
for double-precision arithmetic, in addition to the single-precision functional units used for …
for double-precision arithmetic, in addition to the single-precision functional units used for …
Modified fused multiply and add for exact low precision product accumulation
N Brunie - 2017 IEEE 24th Symposium on Computer Arithmetic …, 2017 - ieeexplore.ieee.org
The implementation of the Fused Multiply and Add (FMA) operation has been extensively
studied in the literature on standard and large precisions. We suggest re-visiting those …
studied in the literature on standard and large precisions. We suggest re-visiting those …
Chained split execution of fused compound arithmetic operations
T Elmer, NA Patil - US Patent 11,061,672, 2021 - Google Patents
A microprocessor is configured for unchained and chained modes of split execution of a
fused compound arithmetic operation. In both modes of split execution, a first execution unit …
fused compound arithmetic operation. In both modes of split execution, a first execution unit …
P6 binary floating-point unit
SD Trong, M Schmookler, EM Schwarz… - … IEEE Symposium on …, 2007 - ieeexplore.ieee.org
The floating point unit of the next generation PowerPC is detailed. It has been tested at over
5 GHz. The design supports an extremely aggressive cycle time of 13 FO4 using a …
5 GHz. The design supports an extremely aggressive cycle time of 13 FO4 using a …
Effective implementation of edge-preserving filtering on cpu microarchitectures
Y Maeda, N Fukushima, H Matsuo - Applied Sciences, 2018 - mdpi.com
In this paper, we propose acceleration methods for edge-preserving filtering. The filters
natively include denormalized numbers, which are defined in IEEE Standard 754. The …
natively include denormalized numbers, which are defined in IEEE Standard 754. The …
Fast, efficient floating-point adders and multipliers for FPGAs
KS Hemmert, KD Underwood - ACM Transactions on Reconfigurable …, 2010 - dl.acm.org
Floating-point applications are a growing trend in the FPGA community. As such, it has
become critical to create floating-point units optimized for standard FPGA technology …
become critical to create floating-point units optimized for standard FPGA technology …