Forwarding element with a data plane load balancer
J Lee, C Kim - US Patent 10,158,573, 2018 - Google Patents
Some embodiments of the invention provide a forwarding element that has a data-plane
circuit (data plane) that can be configured to implement one or more load balancers. The …
circuit (data plane) that can be configured to implement one or more load balancers. The …
Data-plane stateful processing units in packet processing pipelines
P Bosshart, JES Peterson, MG Ferrara, C Kim… - US Patent …, 2018 - Google Patents
A synchronous packet-processing pipeline whose data paths are populated with data-plane
stateful processing units (DSPUs) is provided. A DSPU is a programmable processor whose …
stateful processing units (DSPUs) is provided. A DSPU is a programmable processor whose …
Configuring a switch for extracting packet header fields
P Bosshart - US Patent 10,225,381, 2019 - Google Patents
(57) ABSTRACT A method for generating configuration data for configuring a hardware
switch is described. The method receives a description of functionality for the hardware …
switch is described. The method receives a description of functionality for the hardware …
Data management system employing a hash-based and tree-based key-value data structure
SN Trika, D Park, P Li, FR Corrado… - US Patent App. 15 …, 2019 - Google Patents
BACKGROUND [0002] Conventional key-value data structures either pro vide fast read/write
capability or fast scanning capability, but not both. For example, a hash-based key-value …
capability or fast scanning capability, but not both. For example, a hash-based key-value …
Data-plane stateful processing units in packet processing pipelines
C Kim, S Licking, AS Kaushalram… - US Patent …, 2018 - Google Patents
A synchronous packet-processing pipeline whose data paths are populated with data-plane
stateful processing units (DSPUs) is provided. A DSPU is a programmable processor whose …
stateful processing units (DSPUs) is provided. A DSPU is a programmable processor whose …
Data-plane stateful processing units in packet processing pipelines
AS Kaushalram, M Budiu, C Kim - US Patent 10,523,764, 2019 - Google Patents
(57) ABSTRACT A synchronous packet-processing pipeline whose data paths are
populated with data-plane stateful processing units (DS PUs) is provided. A DSPU is a …
populated with data-plane stateful processing units (DS PUs) is provided. A DSPU is a …
Variable TCAM actions
KK Immidi - US Patent 10,778,612, 2020 - Google Patents
Described herein are various embodiments of a network element comprising a network port
to receive a unit of network data and a data plane coupled to the network port. In one …
to receive a unit of network data and a data plane coupled to the network port. In one …
Data-plane stateful processing units in packet processing pipelines
C Kim, P Bosshart, JES Peterson… - US Patent App. 15 …, 2018 - Google Patents
A synchronous packet-processing pipeline whose data paths are populated with data-plane
stateful processing units (DSPUs) is provided. A DSPU is a programmable processor whose …
stateful processing units (DSPUs) is provided. A DSPU is a programmable processor whose …
Storing packet data in mirror buffer
PD Bhide, A Loge, C Kodeboyina… - US Patent 10,230,810, 2019 - Google Patents
370/369 2007/0183415 A1 8/2007 Fischer et al. 2008/0247409 Al 10/2008 Choudhury et al.
2010/0088756 A1 4/2010 Balakrishnan et al. 2014/0241361 A1 8/2014 Bosshart et al …
2010/0088756 A1 4/2010 Balakrishnan et al. 2014/0241361 A1 8/2014 Bosshart et al …
Dynamic memory reallocation for match-action packet processing
P Bosshart - US Patent 9,880,768, 2018 - Google Patents
A pool of unit memories is provided in order to flexibly allocate memory capacity to
implement various tables and/or logical memories such as those for implementing an …
implement various tables and/or logical memories such as those for implementing an …