Construction of a technology library for use in an electronic design automation system that converts the technology library into non-linear, gain-based models for …
M Iyer, A Kapoor - US Patent 6,467,068, 2002 - Google Patents
(57) ABSTRACT A System and proceSS for constructing a technology library that is Suitable
for use with an electronic design automation System that converts the target technology …
for use with an electronic design automation System that converts the target technology …
Evaluation of a technology library for use in an electronic design automation system that converts the technology library into non-linear, gain-based models for …
M Iyer, A Kapoor - US Patent 6,446,240, 2002 - Google Patents
An evaluation system for evaluating the suitability of a target technology library for use with
an electronic design automation system that converts the target technology library into a …
an electronic design automation system that converts the target technology library into a …
Non-linear, gain-based modeling of circuit delay for an electronic design automation system
M Iyer, A Kapoor - US Patent 6,543,036, 2003 - Google Patents
(57) ABSTRACT A non-linear, gain-based modeling of circuit delay within an electronic
design automation System. The present invention provides a Scalable cell model for use in …
design automation System. The present invention provides a Scalable cell model for use in …
Delay-bound determination for path constraint satisfaction
N Azemard, M Aline… - Design, Modeling, and …, 2000 - spiedigitallibrary.org
This paper addresses the problem of path constraint satisfaction form delay bound
determination. Based on a path delay profiling tool a method is developed to determine the …
determination. Based on a path delay profiling tool a method is developed to determine the …
Feasible delay bound definition
N Azemard, M Aline, P Maurine, D Auvergne - SOC Design Methodologies …, 2002 - Springer
Minimizing the number of iterations when satisfying performance constraints in IC design is
of fundamental importance to limit the design iterations. We present a method to determine …
of fundamental importance to limit the design iterations. We present a method to determine …
Delay bound determination for timing closure satisfaction
N Azemard, M Aline, D Auvergne - ISCAS 2001. The 2001 IEEE …, 2001 - ieeexplore.ieee.org
Minimizing the number of iterations to satisfy performance constraints when designing
complex circuits implies as well as a good prediction of the place and route interconnect …
complex circuits implies as well as a good prediction of the place and route interconnect …