We present a software tool for power dissipation analysis and optimization on the
algorithmic abstraction level from C/C++ and VHDL descriptions. An analysis is most …

An approach for power modelling of parameterized, technology independent design
components (firm-macros) is presented. Executable simulation models in form of C++ …

Summary form only given. The problem of estimating lower bounds on the power
consumption in scheduled data flow graphs with a fixed number of allocated resources prior …

This paper addresses the problem of estimating lower bounds on the power consumption in
scheduled data flow graphs with a fixed number of allocated resources prior to binding. The …

Power-gating is the most promising run-time technique in order to reduce leakage currents
in sub-100nm CMOS devices but its application is associated with numerous problems …

Different power management techniques have been developed to target leakage-reduction
at runtime of a design by orders of magnitude. To advance an optimization, different power …

SoC designer face two main problems nowadays. Firstly, the complexity of ASICs is
expected to double every 18 months as Moore's Law did not loose its correctness yet …

SoC designers face two main problems nowadays. First, the complexity of ASICs is doubling
every 18 months, following Moore's Law, while the productivity of designers evolves at a …

Consideration of an embedded system's timing behaviour and power consumption at system-
level is increasingly important nowadays but it is also an ambitious task. Sophisticated tools …

This paper describes a new method to integrate low power analysis into high-level
synthesis. We addressed especially a specific analysis technique within the scheduling task …