The scaling of microchip technologies has enabled large scale systems-on-chip (SoC).
Network-on-chip (NoC) research addresses global communication in SoC, involving (i) a …

For more than 20 years, significant research effort was concentrated on globally
asynchronous, locally synchronous (GALS) design methodologies. But despite several …

A method is presented to recover 3D scene structure and camera motion from multiple
images without the need for correspondence information. The problem is framed as finding …

An asynchronous design paradigm is capable of addressing the impact of increased
process variability, power and thermal bottlenecks, high fault rates, aging, and scalability …

This paper gives an overview of state-of-the-art regarding the network-on-chip (NoC)
proposals. NoC paradigm replaces dedicated, design-specific wires with scalable, general …

In this paper, we present an area-efficient, globally asynchronous, locally synchronous
network-on-chip (NoC) architecture for a hard real-time multiprocessor platform. The NoC …

Requiring more bandwidth at reasonable power consumption, new communication
infrastructures must provide adequate solutions to guarantee performance during physical …

To accommodate the growing number of applications integrated on a single chip, Networks
on Chip (NoC) must offer scalability not only on the architectural, but also on the physical …

Flow control mechanisms in Network-on-Chip (NoC) architectures are critical for fast packet
propagation across the network and for low idling of network resources. Buffer management …

In this paper, we propose the design of on-chip and off-chip interfaces adapted to a globally
asynchronous locally synchronous (GALS) network-on-chip (NoC) architecture. The …