A survey on two-dimensional Error Correction Codes applied to fault-tolerant systems

D Freitas, C Marcon, J Silveira, L Naviner… - Microelectronics …, 2022 - Elsevier
The number of memory faults operating in radiation environments increases with the
electronic device miniaturization. One-dimensional (1D) Error Correction Codes (ECCs) are …

A Triple Burst Error Correction Based on Region Selection Code

F Silva, AC Pinheiro, JAN Silveira… - IEEE Transactions on …, 2023 - ieeexplore.ieee.org
The evolution of microelectronics boosts more scalable and complex circuit designs,
providing high processing speed and greater storage capacity. However, reliability issues …

Comparing structures of two-dimensional error correction codes

A Muniz, L Mazzoco, W Savaris, E Pissolatto… - Microelectronics …, 2024 - Elsevier
Advances in integrated circuit production technologies have reduced device sizes, leading
to corresponding scaling in electrical characteristics, such as threshold voltage. This scaling …

A universal, low-delay, SEC-DEC-TAEC code for state register protection

M Dong, W Pan, Z Qiu, X Qi, L Zheng, H Liu - IEEE Access, 2022 - ieeexplore.ieee.org
Finite State Machine (FSM) is widely used in electronic systems and its reliability is critical to
the system. Ionizing radiation induced soft error is one of the major concerns in the design of …

CLC-A: An adaptive implementation of the Column Line Code (CLC) ECC

F Silva, A Muniz, J Silveira… - 2020 33rd Symposium on …, 2020 - ieeexplore.ieee.org
Column-Line-Code (CLC) is an Error Correction Code (ECC) designed to correct multiple
errors in memory devices for critical applications. CLC has originally two decoder modes …

Check-bit Region Exploration in Two-Dimensional Error Correction Codes

D Freitas, D Mota, D Coelho, H Fontinele… - IEEE …, 2024 - ieeexplore.ieee.org
The diversity of nanosatellite applications is increasingly attracting the scientific community's
attention. The main component of these satellites is the OnBoard Computer (OBC), which is …

LPC: An error correction code for mitigating faults in 3D memories

DCC Freitas, DFM Mota, C Marcon… - IEEE Transactions …, 2020 - ieeexplore.ieee.org
The radiation sensitivity of memory cells increases dramatically as CMOS manufacture
technology scales down; therefore, the reliability of memories has become a challenge. 3D …

Interleaved Counter Matrix Code in SRAM Memories for Continuous Adjacent Multiple Bit Upset Correction

A Gorantla, G Kiruba, AA Hamad, MM Hassan… - Journal of Electronic …, 2024 - Springer
SRAM memory systems are suffering from an increase in data due to the aggressive CMOS
integration density. The frequency of Multiple Cell Upsets (MCUs) on SRAM memory is …

OPCoSA: an Optimized Product Code for space applications

D Freitas, J Silveira, C Marcon, L Naviner, J Mota - Integration, 2022 - Elsevier
The integrated circuit shrinkage increases the probability and the number of errors in
memories due to the increase in the sensitivity to electromagnetic radiation. Critical …

New decoding techniques for modified product code used in critical applications

DCC Freitas, C Marcon, JAN Silveira… - Microelectronics …, 2022 - Elsevier
The shrinking of memory devices increased the probability of system failures due to the
higher sensitivity to electromagnetic radiation. Critical memory systems employ fault-tolerant …