Chiplet heterogeneous integration technology—Status and challenges

T Li, J Hou, J Yan, R Liu, H Yang, Z Sun - Electronics, 2020 - mdpi.com
As a heterogeneous integration technology, the chiplet-based design technology integrates
multiple heterogeneous dies of diverse functional circuit blocks into a single chip by using …

[HTML][HTML] The big chip: Challenge, model and architecture

Y Han, H Xu, M Lu, H Wang, J Huang, Y Wang… - Fundamental …, 2024 - Elsevier
Abstract As Moore's Law comes to an end, the implementation of high-performance chips
through transistor scaling has become increasingly challenging. To improve performance …

SPACX: Silicon photonics-based scalable chiplet accelerator for DNN inference

Y Li, A Louri, A Karanth - 2022 IEEE International Symposium …, 2022 - ieeexplore.ieee.org
In pursuit of higher inference accuracy, deep neural network (DNN) models have
significantly increased in complexity and size. To overcome the consequent computational …

Architecture of computing system based on chiplet

G Shan, Y Zheng, C Xing, D Chen, G Li, Y Yang - Micromachines, 2022 - mdpi.com
Computing systems are widely used in medical diagnosis, climate prediction, autonomous
vehicles, etc. As the key part of electronics, the performance of computing systems is crucial …

SPRINT: A high-performance, energy-efficient, and scalable chiplet-based accelerator with photonic interconnects for CNN inference

Y Li, A Louri, A Karanth - IEEE Transactions on Parallel and …, 2021 - ieeexplore.ieee.org
Chiplet-based convolution neural network (CNN) accelerators have emerged as a promising
solution to provide substantial processing power and on-chip memory capacity for CNN …

Ascend: A scalable and energy-efficient deep neural network accelerator with photonic interconnects

Y Li, K Wang, H Zheng, A Louri… - IEEE Transactions on …, 2022 - ieeexplore.ieee.org
The complexity and size of recent deep neural network (DNN) models have increased
significantly in pursuit of high inference accuracy. Chiplet-based accelerator is considered a …

Scaling deep-learning inference with chiplet-based architecture and photonic interconnects

Y Li, A Louri, A Karanth - 2021 58th ACM/IEEE Design …, 2021 - ieeexplore.ieee.org
Chiplet-based architectures have been proposed to scale computing systems for deep
neural networks (DNNs). Prior work has shown that for the chiplet-based DNN accelerators …

Seizing the bandwidth scaling of on-package interconnect in a post-Moore's law world

G Chirkov, D Wentzlaff - … of the 37th International Conference on …, 2023 - dl.acm.org
The slowing and forecasted end of Moore's Law have forced designers to look beyond
simply adding transistors, encouraging them to employ other unused resources as a manner …

Enhancing interconnection network topology for chiplet-based systems: An automated design framework

Z Cao, Q Liu, Z Wan, W Zhang, K Song, W Liu - Future Generation …, 2025 - Elsevier
Chiplet-based systems integrate discrete chips on an interposer and use the interconnection
network to enable communication between different components. The topology of the …

A silicon photonic multi-DNN accelerator

Y Li, A Louri, A Karanth - 2023 32nd International Conference …, 2023 - ieeexplore.ieee.org
In shared environments like cloud-based datacenters, hardware accelerators are deployed
to meet the scale-out computation demands of deep neural network (DNN) inference tasks …