A single-bitline 9T SRAM for low-power near-threshold operation in FinFET technology
Static random-access memories (SRAMs), which are the most ubiquitous in modern system-
on-chips, suffer from high power dissipation and poor stability in advanced complementary …
on-chips, suffer from high power dissipation and poor stability in advanced complementary …
Characterization of half-select free write assist 9T SRAM cell
Modern biomedical applications have created a high demand for low power static random
access memory (SRAM). In this article, a reliable low power half-select free-write assist 9T …
access memory (SRAM). In this article, a reliable low power half-select free-write assist 9T …
Design of a Schmitt-trigger-based 7T SRAM cell for variation resilient low-energy consumption and reliable internet of things applications
E Abbasian, M Gholipour - AEU-International Journal of Electronics and …, 2021 - Elsevier
The internet of things (IoTs)-based systems require battery-enabled energy-efficient memory
circuits to operate at low voltage domain, especially below the transistor's threshold. This …
circuits to operate at low voltage domain, especially below the transistor's threshold. This …
Low leakage fully half-select-free robust SRAM cells with BTI reliability analysis
This paper presents two different topologies of 11T SRAM cells with fully half-select-free
robust operation for bit-interleaving implementation. The proposed 11T-1 and 11T-2 cells …
robust operation for bit-interleaving implementation. The proposed 11T-1 and 11T-2 cells …
Half-select-free low-power dynamic loop-cutting write assist SRAM cell for space applications
Smaller, lighter, and cost-effective satellite design is a major field of research today. Since
such satellites are equipped with limited resources, there is a huge demand for low-power …
such satellites are equipped with limited resources, there is a huge demand for low-power …
A 32 nm single-ended single-port 7T static random access memory for low power utilization
In this paper, a seven-transistor static random access memory (SRAM) bit cell with a single
bitline architecture is proposed. This cell is designed at 32 nm and is operational at 300 mV …
bitline architecture is proposed. This cell is designed at 32 nm and is operational at 300 mV …
A highly stable reliable SRAM cell design for low power applications
The growth in demand for power-efficient neural network accelerators has generated an
intense demand for low power static random access memory (SRAM). In this context, a …
intense demand for low power static random access memory (SRAM). In this context, a …
A schmitt-trigger-based low-voltage 11 T SRAM cell for low-leakage in 7-nm FinFET technology
E Abbasian, E Mani, M Gholipour… - Circuits, Systems, and …, 2022 - Springer
This paper proposes a modified Schmitt-trigger (ST)-based single-ended 11 T (MST11T)
SRAM cell. The proposed cell is best suited to ultra-low voltage applications. Two ST-based …
SRAM cell. The proposed cell is best suited to ultra-low voltage applications. Two ST-based …
Low leakage single bitline 9 t (sb9t) static random access memory
This paper presents a low leakage, half-select free SB9T SRAM cell with good static and
dynamic read/write performance along with smaller area. The proposed cell offers high …
dynamic read/write performance along with smaller area. The proposed cell offers high …
Design of power-and variability-aware nonvolatile RRAM cell using memristor as a memory element
A 3 CNFETs and 2 memristors-based half-select disturbance free 3T2R resistive RAM
(RRAM) cell is proposed in this paper. While the two memristors act as the nonvolatile …
(RRAM) cell is proposed in this paper. While the two memristors act as the nonvolatile …