Hardware verification using software analyzers

R Mukherjee, D Kroening… - 2015 IEEE Computer …, 2015 - ieeexplore.ieee.org
Program analysis is a highly active area of research, and the capacity and precision of
software analyzers is improving rapidly. We investigate the use of modern software …

Effective simulation and debugging for a high-level hardware language using software compilers

C Pit-Claudel, T Bourgeat, S Lau, Arvind… - Proceedings of the 26th …, 2021 - dl.acm.org
Rule-based hardware-design languages (RHDLs) promise to enhance developer
productivity by offering convenient abstractions. Advanced compiler technology keeps the …

Bridging Hardware and Software Analysis with Btor2C: A Word-Level-Circuit-to-C Translator

D Beyer, PC Chien, NZ Lee - … Conference on Tools and Algorithms for the …, 2023 - Springer
Across the broad research field concerned with the analysis of computational systems,
research endeavors are often categorized by the respective models under investigation …

v2c–A verilog to C translator

R Mukherjee, M Tautschnig, D Kroening - … , TACAS 2016, Held as Part of …, 2016 - Springer
We present v2c, a tool for translating Verilog to C. The tool accepts synthesizable Verilog as
input and generates a word-level C program as an output, which we call the software netlist …

Maintaining consistency between SystemC and RTL system designs

A Bruce, MM Kamal Hashmi, A Nightingale… - Proceedings of the 43rd …, 2006 - dl.acm.org
We describe how system design consistency can be maintained across multiple levels of
design abstraction using a modular verification IP strategy. This strategy involves delivery of …

Verifying RISC-V Privilege Transition Integrity Through Symbolic Execution

S Tang, J Zhu, Y Gao, J Zhou, D Mu… - 2023 IEEE 32nd Asian …, 2023 - ieeexplore.ieee.org
Ensuring privilege transition integrity during execution context switch is crucial for protecting
the processor from unauthorized access and malicious actions. However, existing methods …

[PDF][PDF] Formal Verification of Hardware using MLIR

A Dobis - 2024 - research-collection.ethz.ch
Modern hardware development is increasingly turning to high-level hardware construction
languages to speed up hardware development. CIRCT aims to unify these languages into a …

A spatial computing architecture for implementing computational circuits

D Grant, GGF Lemieux - 2008 1st Microsystems and …, 2008 - ieeexplore.ieee.org
To accelerate many computational software algorithms, designers are implementing them as
computational circuits. These algorithms are diverse and include molecular dynamics …

An SMT-Based Reverse Engineering of Register Allocation in High-Level Synthesis

M Abderehman, C Karfa - … Electronic Devices, Circuits and Systems: Select …, 2023 - Springer
The variables of a high-level behaviour are mapped to hardware registers during register
allocation (RA) in high-level synthesis (HLS). Reverse engineering such mapping is a …

Precise abstract interpretation of hardware designs

R Mukherjee - 2018 - ora.ox.ac.uk
This dissertation shows that the bounded property verification of hardware Register Transfer
Level (RTL) designs can be efficiently performed by precise abstract interpretation of a …