Warped-compression: Enabling power efficient GPUs through register compression

S Lee, K Kim, G Koo, H Jeon, WW Ro… - ACM SIGARCH …, 2015 - dl.acm.org
This paper presents Warped-Compression, a warp-level register compression scheme for
reducing GPU power consumption. This work is motivated by the observation that the …

Warped register file: A power efficient register file for GPGPUs

M Abdel-Majeed, M Annavaram - 2013 IEEE 19th International …, 2013 - ieeexplore.ieee.org
General purpose graphics processing units (GPGPUs) have the ability to execute hundreds
of concurrent threads. To support massive parallelism GPGPUs provide a very large register …

A survey of techniques for designing and managing CPU register file

S Mittal - Concurrency and Computation: Practice and …, 2017 - Wiley Online Library
Processor register file (RF) is an important microarchitectural component used for storing
operands and results of instructions. The design and operation of RF have crucial impact on …

On the characterization and optimization of on-chip cache reliability against soft errors

S Wang, J Hu, SG Ziavras - IEEE Transactions on Computers, 2009 - ieeexplore.ieee.org
Soft errors induced by energetic particle strikes in on-chip cache memories have become an
increasing challenge in designing new generation reliable microprocessors. Previous efforts …

Improving energy efficiency of GPUs through data compression and compressed execution

S Lee, K Kim, G Koo, H Jeon… - IEEE Transactions …, 2016 - ieeexplore.ieee.org
GPU design trends show that the register file size will continue to increase to enable even
more thread level parallelism. As a result register file consumes a large fraction of the total …

Studying the evolution of open source systems at different levels of granularity: Two case studies

A Capiluppi, JF Ramil - Proceedings. 7th International …, 2004 - ieeexplore.ieee.org
This work presents a study of several evolutionary attributes of two open source software
systems: the distributed file system Arla and the stable branch of the Web browser Mozilla …

Energy-efficient register caching with compiler assistance

TM Jones, MFP O'Boyle, J Abella, A González… - ACM Transactions on …, 2009 - dl.acm.org
The register file is a critical component in a modern superscalar processor. It must be large
enough to accommodate the results of all in-flight instructions. It must also have enough …

Adaptive reorder buffers for SMT processors

J Sharkey, D Balkan, D Ponomarev - Proceedings of the 15th …, 2006 - dl.acm.org
In SMT processors, the complex interplay between private and shared datapath resources
needs to be considered in order to realize the full performance potential. In this paper, we …

Operand width aware hardware reuse: a low cost fault-tolerant approach to ALU design in embedded processors

M Fazeli, A Namazi, SG Miremadi… - Microelectronics …, 2011 - Elsevier
This paper presents a low cost fault-tolerant technique so called OWHR (Operand Width
Aware Hardware Reuse) to ALU design in embedded processors. The OWHR technique is …

An area-efficient approach to improving register file reliability against transient errors

M Kandala, W Zhang, LT Yang - 21st International Conference …, 2007 - ieeexplore.ieee.org
This paper studies approaches to exploiting the space both within or across registers
efficiently for improving the register file reliability against transient errors. The idea of our …