A 10-Gb/s low jitter single-loop clock and data recovery circuit with rotational phase frequency detector
FT Chen, MS Kao, YH Hsu, JM Wu… - … on Circuits and …, 2014 - ieeexplore.ieee.org
This paper presents a rotational phase frequency detector (RPFD) for reference-less clock
and data recovery circuit (CDR). The proposed RPFD changes the bang-bang phase …
and data recovery circuit (CDR). The proposed RPFD changes the bang-bang phase …
ESD design strategies for high-speed digital and RF circuits in deeply scaled silicon technologies
S Cao, JH Chun, SG Beebe… - IEEE Transactions on …, 2010 - ieeexplore.ieee.org
Challenges of electrostatic discharge (ESD) protection in deeply scaled silicon technologies
are addressed by improving design, characterization, and modeling of I/O MOSFETs …
are addressed by improving design, characterization, and modeling of I/O MOSFETs …
A 2.5-Gb/s DLL-Based Burst-Mode Clock and Data Recovery Circuit With Oversampling
JM Lin, CY Yang, HM Wu - IEEE Transactions on Very Large …, 2014 - ieeexplore.ieee.org
In this brief, a delay-locked loop (DLL)-based burst-mode clock and data recovery (BMCDR)
circuit using a 4× oversampling technique is realized for passive optical network. With the …
circuit using a 4× oversampling technique is realized for passive optical network. With the …
A super-regenerative ASK receiver with ΔΣ pulse-width digitizer and SAR-based fast frequency calibration for MICS applications
This paper presents a 400MHz super-regenerative receiver (SR-RX) with a proposed
ΔΣpulse-width digitizer (ΔΣ-PWD) and a SAR-based fast frequency calibration (SAR-FFC) …
ΔΣpulse-width digitizer (ΔΣ-PWD) and a SAR-based fast frequency calibration (SAR-FFC) …
Methods for calibrating gated oscillator and oscillator circuit utilizing the same
An oscillator circuit is provided. The oscillator circuit includes a gated oscillator and a
calibration circuit. The gated oscillator is arranged to generate an oscillator signal according …
calibration circuit. The gated oscillator is arranged to generate an oscillator signal according …
A reference-free, digital background calibration technique for gated-oscillator-based CDR/PLL
A background calibration technique for gated-oscillator-based CDR/PLL is presented. This
digital approach eliminates the frequency offset between the gated oscillator and the input …
digital approach eliminates the frequency offset between the gated oscillator and the input …
A 10-Gb/s, 1.24 pJ/bit, burst-mode clock and data recovery with jitter suppression
A burst mode clock and data recovery (BMCDR) circuit for 10 Gbps passive optical network
(10G-PON) is presented. The proposed BMCDR is reconfigurable between data gating …
(10G-PON) is presented. The proposed BMCDR is reconfigurable between data gating …
An area-and power-efficient half-rate clock and data recovery circuit
This paper presents a 3.2 Gb/s low-power clock and data recovery (CDR). The improved
architecture using two half-rate gated voltage-controlled oscillators (GVCOs) shared …
architecture using two half-rate gated voltage-controlled oscillators (GVCOs) shared …
[PDF][PDF] A 20 Gb/s Injection-Locked Clock and Data Recovery Circuit
S Jafarbeiki, K Hajsadeghi, N Modir - International Journal of VLSI …, 2014 - academia.edu
This paper presents a 20 Gb/s injection-locked clock and data recovery (CDR) circuit for
burst mode applications. Utilizing a half rate injection-locked oscillator (ILO) in the proposed …
burst mode applications. Utilizing a half rate injection-locked oscillator (ILO) in the proposed …
A 1.08-Gb/s burst-mode clock and data recovery circuit using the jitter reduction technique
A 1.08-Gb/s CMOS half-rate burst-mode clock and data recovery (BMCDR) circuit with a
novel jitter reduction technique is presented. There are several discrete delay time values in …
novel jitter reduction technique is presented. There are several discrete delay time values in …