A 6-to-7.5-GHz 54-fsrms Jitter Type-II Reference-Sampling PLL Featuring a Gain-Boosting Phase Detector for In-Band Phase-Noise Reduction
This paper presents a type-II reference-sampling (RS) phase-locked loop (PLL) exploiting a
novel gain-boosting reference-sampling phase detector (RSPD) to reduce the in-band …
novel gain-boosting reference-sampling phase detector (RSPD) to reduce the in-band …
A 2.4-GHz Multiphase Inductorless PLL With Coupled-Ring Oscillators and Time-Amplifying Phase–Frequency Detector for Low Phase Noise and Robust Locking …
Y Huo, FF Dai - IEEE Microwave and Wireless Technology …, 2024 - ieeexplore.ieee.org
This letter presents an inductorless compact 12-phase integer-N phase-locked-loop (PLL)
with time-amplifying phase-frequency detector (TAPFD) to achieve low in-band phase noise …
with time-amplifying phase-frequency detector (TAPFD) to achieve low in-band phase noise …
An RC-Based Dual Injection Locked Delay Cell for High-Frequency Ring VCOs
This paper proposes an RC-based dual injection-locked (RC-DIL) delay cell for a coupled
ring voltage-controlled oscillator (RVCO). The RC-DIL delay cell uses an RC network …
ring voltage-controlled oscillator (RVCO). The RC-DIL delay cell uses an RC network …
A Fully Synthesizable DPLL with Background Gain Mismatch Calibrated Feedforward Phase Noise Cancellation Path
This work presents a fully synthesizable DPLL with a feedforward phase noise cancellation
(FPNC) path. The gain mismatch between the FPNC path components has been calibrated …
(FPNC) path. The gain mismatch between the FPNC path components has been calibrated …
A 20.8-23.2 GHz sub-sampling PLL with transformer-coupled VCO feedback loop achieving-47.05 dBc reference spur and-245.9 dB FOM in 40nm CMOS technology
Z Zhang, W Zheng, X Xia, Y Wang - IEICE Electronics Express, 2023 - jstage.jst.go.jp
Abstract This paper presents a 20.8–23.2 GHz integer-N sub-sampling phase-locked loop
(SSPLL) with low-reference spur and low-phase noise. A transformer-coupled based voltage …
(SSPLL) with low-reference spur and low-phase noise. A transformer-coupled based voltage …
A High-Linearity 19 GHz LC-Based VCO for PVT Compensation
T Li, Y Zhan, L Zhang, X Zou… - 2024 IEEE 7th …, 2024 - ieeexplore.ieee.org
A high-linearity 19 GHz LC-based VCO circuit with PVT compensation was designed, which
can achieve a low-jitter high-quality clock signal. Cross-coupled PMOS-NMOS structure with …
can achieve a low-jitter high-quality clock signal. Cross-coupled PMOS-NMOS structure with …