[PDF][PDF] Implementation of Low Power and area efficient carry select Adder

PR Hotkar, V Kulkarni, P Kamble… - International Journal of …, 2019 - researchgate.net
Design of low area and low power forms the largest systems in VLSI system design. Carry
Select Adder (CSLA) is one of the fastest adders to perform arithmetic operations comparing …

Design of carry select adder using logic optimization technique

M Sreevani, S Lakshmanachari… - … on Advances in …, 2021 - ieeexplore.ieee.org
Carry Select Adder (CSLA) is an essentially utilized adder on account of its higher
computational speed. CSLA is utilized in the space of incorporation frameworks. This paper …

High-speed and energy efficient carry select adder (CSLA) dominated by carry generation logic

M Nam, Y Choi, K Cho - Microelectronics Journal, 2018 - Elsevier
This paper presents a high-speed, energy efficient carry select adder (CSLA) dominated by
carry generation logics. The proposed architecture is composed of three functional stages–a …

Design of area efficient VLSI architecture for carry select adder using logic optimization technique

BS Kandula, PV Kalluru, SP Inty - Computational Intelligence, 2021 - Wiley Online Library
Abstract Square Root Carry Select Adder (SQRT‐CSLA) is accomplishing the noteworthy
attention in the arena of VLSI (Very‐Large‐Scale Integration) systems as it can process the …

A new high-speed and low area efficient pipelined 128-bit adder based on modified carry look-ahead merging with Han-Carlson tree method

S Ghafari, M Mousazadeh, A Khoei… - 2019 MIXDES-26th …, 2019 - ieeexplore.ieee.org
In this paper, a 128-bit pipeline Adder is presented, in the form of a syntactic Tree Adder by
an introduction of a new modified Carry-Look-Ahead (CLA) that is merged inside the Tree …

A 90 nm area and power efficient Carry Select Adder using 2–1 multiplexer based Excess-1 block

B Jeevan, K Bikshalu, K Sivani - Engineering Research Express, 2023 - iopscience.iop.org
This paper proposes a novel architecture of excess-1 adder-based Carry Select Adder
(M2CSA) using single leaf cell ie, 2–1 Multiplexer. M2CSA is designed using a new type of …

High-speed and low-cost carry select adders utilizing new optimized add-one circuit and multiplexer-based logic

MA Rudposhti, M Valinataj - Integration, 2021 - Elsevier
In this paper, we propose some SQuare-RooT (SQRT) Carry SeLect Adder (CSLA)
architectures including a high-speed design, a design with the lowest area compared to …

Design of high-performance carry select adder using multiplexer based logic in 90nm technology

KJ Wesly, S Rajesh, MR Rajeswaran… - 2023 4th …, 2023 - ieeexplore.ieee.org
To design a high-speed SqRt CSLA (Square Root Carry Select Look Ahead Adder) by using
Multiplexer logic in order to reduce the number of gates. Performance comparison of …

A novel area-delay efficient carry select adder based on new add-one circuit

MA Roodposhti, M Valinataj - 2019 9th International …, 2019 - ieeexplore.ieee.org
In this paper, a new carry select adder (CSLA) architecture is proposed with a lower area
and a higher speed compared to previous CSLAs. The proposed CSLA is a low-area and …

Efficiency and Speed Trade-Offs in 8-Bit CMOS Adders at 180nm: An In-Depth Examination

A Ravindran, A George, AM George… - … on Recent Advances …, 2023 - ieeexplore.ieee.org
This paper analyses the performance of different adders in terms of power delay and area.
Adders are fundamental units in arithmetic circuits. Adders, till now, have undergone several …