Sequential and parallel solution-biased search for subgraph algorithms

B Archibald, F Dunlop, R Hoffmann… - … on Integration of …, 2019 - Springer
The current state of the art in subgraph isomorphism solving involves using degree as a
value-ordering heuristic to direct backtracking search. Such a search makes a heavy …

Between subgraph isomorphism and maximum common subgraph

R Hoffmann, C McCreesh, C Reilly - … of the AAAI Conference on Artificial …, 2017 - ojs.aaai.org
When a small pattern graph does not occur inside a larger target graph, we can ask how to
find" as much of the pattern as possible" inside the target graph. In general, this is known as …

An efficient subgraph isomorphism solver for large graphs

ZA Ansari, M Abulaish - IEEE Access, 2021 - ieeexplore.ieee.org
For a given pair of pattern and data graphs, the subgraph isomorphism finding problem
locates all instances of the pattern graph into the data graph. For a given subgraph …

Instruction Selection

GH Blindell - Principles, Methods, and Applications, 2016 - Springer
Like most doctoral students, I started my studies by reviewing the existing, most prominent
approaches in the field. A couple of months later I thought I had acquired a sufficient …

Solving hard subgraph problems in parallel

C McCreesh - 2017 - theses.gla.ac.uk
This thesis improves the state of the art in exact, practical algorithms for finding subgraphs.
We study maximum clique, subgraph isomorphism, and maximum common subgraph …

Pre-architectural performance estimation for ASIP design based on abstract processor models

JF Eusse, C Williams, LG Murillo… - 2014 International …, 2014 - ieeexplore.ieee.org
Application Specific Instruction Set Processors (ASIPs) seek for an optimal
performance/area/energy trade-off for a given algorithm. In all current design methodologies …

Virtual prototype driven design, implementation and evaluation of risc-v instruction set extensions

M Funck, V Herdt, R Drechsler - 2022 25th International …, 2022 - ieeexplore.ieee.org
RISC-V is a modern open source Instruction Set Architecture (ISA) and designed in a very
extendable manner, which allows for highly application specific solutions. However, the …

[PDF][PDF] ISTANBUL TECHNICAL UNIVERSITY 击GRADUATE SCHOOL

L AKÇAY - 2022 - polen.itu.edu.tr
The study is introduced under four main sections in this chapter. First, the purpose of the
thesis is explained clearly. Afterwards, a detailed literature review is given in order to …

Instruction extension of a risc-v processor modeled with ip-xact

S Payvar, E Pekkarinen, R Stahl… - 2019 IEEE Nordic …, 2019 - ieeexplore.ieee.org
Short time-to-market and cost consideration of hardware design promotes reuse of ever
more complex intellectual property even up to processors. In processor design, the …

Free rider: A tool for retargeting platform-specific intrinsic functions

S Manilov, B Franke, A Magrath, C Andrieu - Acm sigplan notices, 2015 - dl.acm.org
Short-vector SIMD and DSP instructions are popular extensions to common Isas. These
extensions deliver excellent performance and compact code for some compute-intensive …