Graphene nanoribbons (GNRs) have recently emerged as promising candidates for channel
materials in future nanoelectronic devices due to their exceptional electronic, thermal, and …

Copper interconnects in modern integrated circuits require a barrier layer to prevent Cu
diffusion into surrounding dielectrics. However, conventional barrier materials like TaN are …

The interconnect half‐pitch size will reach≈ 20 nm in the coming sub‐5 nm technology
node. Meanwhile, the TaN/Ta (barrier/liner) bilayer stack has to be> 4 nm to ensure …

Due to its ultrathin feature, graphene has been recently proposed as diffusion barrier layer
for Cu wires. This paper is geared toward developing an equivalent single-conductor (ESC) …

Reliability of 80-, 100-, and 120-nm wide copper interconnects is improved using in situ
grown graphene as a capping material. The graphene-capped Cu wires exhibit 2.4-3.5× …

An integrated circuit (IC), or chip, is a set of electronic circuits and components placed on a
tiny planar silicon (Si) semiconductor substrate. These electronics circuits and components …

A different mechanism was found for Cu transport through multi-transferred single-layer
graphene serving as diffusion barriers on the basis of time-dependent dielectric breakdown …

To maintain the scaling trends in the complementary metal oxide semiconductor (CMOS)
technology, the thickness of barrier/liner systems used in back-end-of-line (BEOL) …

The scaling limit of conventional Cu diffusion barriers has become the bottleneck for
interconnect technology, which in turn limits the IC performance. Sub-nm diffusion barrier is …

With device scaling facing major physical and manufacturing challenges, many research
efforts have been focused on the impact of device parameters and designs on circuit …