Reliability metrics for hardware faults in safety-/mission-critical systems have been
historically based solely on hardware failure rates, quantitatively ignoring any effect of the …

In this article, a fault-tolerant network-on-chip (NoC) router architecture is introduced. This
article reports a comprehensive fault study of a NoC router through a simulation-based …

This paper presents comparison of transient fault effects in an asynchronous NoC router and
a synchronous one. The experiment is based on simulation-based fault injection method to …

This paper presents a simulation-based fault injection analysis of a MIPS-based dual-core
processor. In order to fulfill the requirement of this analysis, 114 different fault targets are …

In real world Wireless Sensor Network (WSN) applications nodes can be affected by soft
errors that occur either accidentally or are introduced deliberately. Especially when WSNs …

Network-on-Chip (NoC) are known as the future communication infrastructure for many-core
systems. They are susceptible to malfunction in the presence of the faults as technology …

Many-core systems are of great importance for building the exascale computing machine
targeted for 2020. Last-Level Cache (LLC), as the largest on-chip shared memory in many …

Technology scaling and higher operational frequencies are no longer sustainable at the
same pace as before. The processor industry is rapidly moving from a single core with high …

Like every other major changes in computer architecture, exascale computing, targeted for
2020, requires dramatic and unanticipated shifts in different perspectives. The biggest …