With the increasing prevalence of warehouse-scale (WSC) and cloud computing,
understanding the interactions of server applications with the underlying microarchitecture …

We present Decoupled Vector Runahead (DVR), an in-core prefetching technique,
executing separately to the main application thread, that exploits massive amounts of …

The trend of unsustainable power consumption and large memory bandwidth demands in
massively parallel multicore systems, with the advent of the big data era, has brought upon …

Many modern workloads compute on large amounts of data, often with irregular memory
accesses. Current architectures perform poorly for these workloads, as existing prefetching …

The continuous growth of main memory size allows modern data systems to process entire
large scale datasets in memory. The increase in memory capacity, however, is not matched …

Searches on large graphs are heavily memory latency bound, as a result of many high
latency DRAM accesses. Due to the highly irregular nature of the access patterns involved …

Many modern data processing and HPC workloads are heavily memory-latency bound. A
tempting proposition to solve this is software prefetching, where special non-blocking loads …

Applications with irregular memory accesses and control flow, such as graph algorithms and
sparse linear algebra, use high-performance cores very poorly and suffer from dismal IPC …

Irregular applications, such as graph analytics and sparse linear algebra, exhibit frequent
indirect, data-dependent accesses to single or short sequences of elements that cause high …

With the end of Dennard scaling, architects have increasingly turned to special-purpose
hardware accelerators to improve the performance and energy efficiency for some …